cypress register: PRI_SEL_TBL_CTRL
Details
- Name
- PRI_SEL_TBL_CTRL
- Offset
- 10d0
- Feature
- INGRESS_PRIORITY_DECISION
- Array index range
- 0 - 3
- Portlist index
- 0
- Bit offset
- 32
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 27 | 5 |
|
| PROTO_VLAN_WT | 24 | 3 |
|
| RESERVED | 23 | 1 |
|
| MAC_VLAN_WT | 20 | 3 |
|
| RESERVED | 19 | 1 |
|
| OTAG_WT | 16 | 3 |
|
| RESERVED | 15 | 1 |
|
| ITAG_WT | 12 | 3 |
|
| RESERVED | 11 | 1 |
|
| DSCP_WT | 8 | 3 |
|
| RESERVED | 7 | 1 |
|
| ING_ACL_WT | 4 | 3 |
|
| RESERVED | 3 | 1 |
|
| PORT_WT | 0 | 3 |
|