longan register: I2C_MST1_CTRL2
Details
- Name
- I2C_MST1_CTRL2
- Offset
- 0370
- Feature
- INTERFACE
Description
I2C master 1 controller register 2
default: 0x0000_5003
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 25 | 7 |
|
| I2C_RESET | 24 | 1 |
send I2C reset command before each start TBD: Is this the ‘I2C restart’ state?
|
| DRIVE_ACK_DELAY | 20 | 4 |
I2C ACK delay bit Delay before sending an ACK bit to a slave. Delay acknowledgement by N. delay = N * (1/I2C_SCL) |
| CHECK_ACK_DELAY | 16 | 4 |
I2C receive ACK delay bit Time to delay before the slave’s ACK bit. Delay acknowledgement by N. delay = N * (1/I2C_SCL) |
| I2C_RD_MODE | 15 | 1 |
I2C Read Command Mode Standard mode is Write + Address + Read + Data Legacy mode is Read + Address + Data
|
| DEV_ADDR | 8 | 7 |
Device Address The address of the I2C device on the I2C bus, e.g. 0x50 for the standard address of an EEPROM on an SFP module. |
| DATA_WIDTH | 4 | 4 |
I2C command read/write data width (number of bytes) How much data is to be read or written. bytes = N + 1 The controller is able to see that no data is being returned (slave sends NACK) which does not cause an error if DATA_WIDTH is 0. |
| MEM_ADDR_WIDTH | 2 | 2 |
Width of the memory address SMBus command byte(s).
|
| SCL_FREQ | 0 | 2 |
Frequency of the SCL bus:
|