longan register: L3_IPUC_ROUTE_CTRL
Details
- Name
- L3_IPUC_ROUTE_CTRL
- Offset
- ab4c
- Feature
- LAYER_3_ROUTING
Description
Control register for UC routing: Reset value 0x00002000.
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 20 | 12 |
|
| PKT_TO_CPU_TARGET | 19 | 1 |
0: CPU target is local, 1: CPU target is master |
| TTL_FAIL_ACT | 17 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU |
| MTU_FAIL_ACT | 15 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU |
| HDR_OPT_ACT | 12 | 3 |
0: DROP, 1: TRAP2CPU, 2: FORWARD (i.e. route), 3: COPY2CPU (route & copy to CPU), 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU (i.e. route and copy to master) |
| DMAC_MC_ACT | 9 | 3 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU, 3: FORWARD (i.e. bridge), 4: COPY2CPU, 5: COPY2MASTERCPU |
| DMAC_BC_ACT | 7 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU, 3: FORWARD (i.e. bridge) |
| ZERO_SIP_ACT | 5 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU |
| BAD_DIP_ACT | 3 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU |
| BAD_SIP_ACT | 1 | 2 |
0: DROP, 1: TRAP2CPU, 2: TRAP2MASTERCPU |
| GLB_EN | 0 | 1 |
1: Routing enabled |