longan register: P0_INTF_CTRL
Details
- Name
- P0_INTF_CTRL
- Offset
- 0024
- Feature
- INTERFACE
- Port index range
- 0 - 27
- Portlist index
- 0
- Bit offset
- 6
Description
Port N interface controller
default: 0x0000_0000
Fields
Name |
LSB |
Bits |
Description |
P0_INTF |
0 |
6 |
-
TX_SYNC (bit 0)
- 0b0: no SERDES to MAC delay
- 0b1: 1 clock cycle SERDES to MAC delay
-
RX_SYNC (bit 1)
- 0b0: no SERDES to MAC delay
- 0b1: 1 clock cycle SERDES to MAC delay
-
CARRIER_SENSE (bit 2)
-
TXC_EDGE (bit 3)
- 0b0: postitive edge
- 0b1: negative edge
-
RXC_EDGE (bit 4)
- 0b0: postitive edge
- 0b1: negative edge
-
TX_COLLISION (bit 5)
|