longan register: PIE_BLK_PHASE_CTRL
Details
- Name
- PIE_BLK_PHASE_CTRL
- Offset
- a5a4
- Feature
- PIE_TEMPLATE
- Array index range
- 0 - 15
- Portlist index
- 0
- Bit offset
- 1
Description
Assigns a PIE rule block to either the IACL (0) or VACL (1) phase.
Equivalent of the CYPRESS_ACL_CTRL control register but gives more control to mix phases between blocks.
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| PHASE | 0 | 1 |
|