longan register: RST_GLB_CTRL_0
Details
- Name
- RST_GLB_CTRL_0
- Offset
- 000c
- Feature
- RESET
Description
Global Reset Control
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 19 | 13 |
|
| RST_OUT_TMR | 11 | 8 |
Pulse length of reset_out pin val * 1ms (def. 10ms) |
| FRC_RSTOUT | 10 | 1 |
reset_out level
|
| FRC_RSTOUT_EN | 9 | 1 |
reset_pinout enable
|
| CHIP_RST_EN | 8 | 1 |
Use reset_out pin during chip reset
|
| WD_RST_EN | 7 | 1 |
Use reset_out pin during watchdog timeout
|
| SDS_REG_RST | 6 | 1 |
Trigger SerDeS register controller reset
|
| SW_RST | 5 | 1 |
Trigger SwitchCore reset
|
| CPU_MEM_RST | 4 | 1 |
Trigger memory controller reset
|
| SW_SERDES_RST | 3 | 1 |
Trigger SwitchCore SerDeS reset
|
| SW_NIC_RST | 2 | 1 |
Trigger NIC controller reset
|
| SW_Q_RST | 1 | 1 |
Trigger SwitchCore Buffer/Packet Queue reset
|
| SW_CHIP_RST | 0 | 1 |
Trigger full chip reset
|