longan table: LAG
Details
- Name
- LAG
- Feature
- LINK_AGGREGATION
- Type
- 7
- Entries
- 64
- Data width
- 96
- Control register
- TBL_ACCESS_CTRL_1
- Data register
- TBL_ACCESS_DATA_1
Fields
| Name |
LSB |
Bits |
Description |
| NUM_TX_CANDI |
89 |
4 |
|
| L2_HASH_MSK_IDX |
88 |
1 |
|
| IP4_HASH_MSK_IDX |
87 |
1 |
|
| IP6_HASH_MSK_IDX |
86 |
1 |
|
| SEP_DLF_BCAST_EN |
85 |
1 |
|
| SEP_KWN_MC_EN |
84 |
1 |
|
| TRK_DEV7 |
80 |
4 |
|
| TRK_PORT7 |
74 |
6 |
|
| TRK_DEV6 |
70 |
4 |
|
| TRK_PORT6 |
64 |
6 |
|
| TRK_DEV5 |
58 |
4 |
|
| TRK_PORT5 |
52 |
6 |
|
| TRK_DEV4 |
48 |
4 |
|
| TRK_PORT4 |
42 |
6 |
|
| TRK_DEV3 |
38 |
4 |
|
| TRK_PORT3 |
32 |
6 |
|
| TRK_DEV2 |
26 |
4 |
|
| TRK_PORT2 |
20 |
6 |
|
| TRK_DEV1 |
16 |
4 |
|
| TRK_PORT1 |
10 |
6 |
|
| TRK_DEV0 |
6 |
4 |
|
| TRK_PORT0 |
0 |
6 |
|