maple register: PLL_LX_CTRL0
Details
- Name
- PLL_LX_CTRL0
- Offset
- 0fd0
- Feature
- PLL_BIAS
Description
Lexra clock control register.
This is a protected register, with reads and writes protected by the respective bits in INT_RW_CTRL.
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| LX_CMU_FCODE_IN | 20 | 12 |
|
| LX_CMU_DIVN2 | 12 | 8 |
|
| LX_CMU_NCODE_IN | 4 | 8 |
|
| LX_CMU_BYPASS_PI | 3 | 1 |
|
| LX_CMU_SEL_DIV4 | 2 | 1 |
|
| LX_CMU_SEL_PREDIV | 0 | 2 |
|