maple register: PLL_LX_CTRL1
Details
- Name
- PLL_LX_CTRL1
- Offset
- 0fd4
- Feature
- PLL_BIAS
Description
Lexra clock control register.
This is a protected register, with reads and writes protected by the respective bits in INT_RW_CTRL.
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 29 | 3 |
|
| LX_CMU_DIVN3_SEL | 27 | 2 |
|
| LX_CMU_DIVN2_SELB | 26 | 1 |
|
| LX_CMU_EN_SSC | 25 | 1 |
|
| LX_CMU_STEP_IN | 12 | 13 |
|
| LX_CMU_TBASE_IN | 0 | 12 |
|