maple register: SCHED_Q_EGR_RATE_CTRL
Details
- Name
- SCHED_Q_EGR_RATE_CTRL
- Offset
- c00c
- Feature
- SCHEDULING
- Port index range
- 0 - 28
- Array index range
- 0 - 7
- Portlist index
- 0
- Bit offset
- 32
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 18 | 14 |
|
| Q_EGR_RATE | 0 | 18 |
|