Differences

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--- dgs-1210-10p [2020/08/29 08:04] – bkoblitz
+++ dgs-1210-10p [2022/04/25 15:52] (current) – Tag with JTAG svanheule
@@ Line 1: / Line 1: @@
-=== D-Link DGS-1210-10P ===
+====== D-Link DGS-1210-10P (rev F, R) ======
-{{wiki:dgs-1210-10p.png?200}}
+{{ wiki:dgs-1210-10p.png?200}}
-The DGS-1210-10P is a 8 + 2-port Gigabit L2 switch with up to 65 Watts of PoE power on the 8 Gigabit ports. 2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules. It has an [[RTL8380M]] SoC with 8 built-in PHYs, and a [[RTL8231]] GPIO extender to control the port LEDs, system LED, a reset button and a mode switch button for the PoE. Both buttons are software controlled. Power is supplied via a 54V 2A barrel connector.
+The DGS-1210-10P (rev F, R) is a 8 + 2-port Gigabit L2 switch with up to 65 Watts of PoE power on the 8 Gigabit ports. This model is part of the [[DGS-1210 series]] line-up.
-A Serial header is found at J3. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
-PoE is controlled by a Broadcom BCM59121B0KMLG via a Nuvoton ARM microcontroller, which in turn talks a serial protocol with the RTL8380M (19200 baud, 8N1). The exchange between the ARM microcontroller and the RTL SoC can be snooped by connecting a logic analyzer to header J9. Square pin is 3.3V, the middle pins are TX from SoC and ARM chip respectively, the pin opposite of Vcc is GND. J10 is an SWD header to program the Nuvoton Chip.
+===== Hardware =====
+  * [[rtl838x|RTL8380M]] SoC
+  * Macronix MX25L25635F (32 MiB flash)
+  * 128 MiB (256 MiB Nanya NT5CC256M8JQ-EK on R1) RAM
+  * [[rtl8231|RTL8231]] GPIO extender to control the port LEDs, system LED, SFP auxiliary signals, a reset button and a mode switch button for the PoE. Both buttons are software controlled.
+  * Nuvoton M0516LDE ARM microcontroller to service the PoE controller
+  * Broadcom BCM59121B0KMLG PoE controller
-It ships with a bootloader based on Realtek's SDK for RTL83xx SoCs and Linux 2.6 based on Realtek's SDK. It has a web interface for all management functions.
+ Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
-== OpenWRT Support ==
+Power is supplied via a 54V 1.6A barrel connector. PoE budget is 65 W with 30 W maximum per port.
-There is complete hardware support in an experimental OpenWRT branch. Of the L2 features, port isolation, 4096 VLANs, Local Port Mirroring, EEE are supported. There is support to do a basic configuration of PoE, advanced features such as prioritizing power for ports is not supported so far. Media change is detected on the SFP cages for fibre optic cables, however after hot-swapping an SFP module, manual setup is needed. There is no support to read the SFP ID/Sensor data via I2C.
-Original features such as cable integrity tests, offloaded remote mirroring and Port-ACLs are not yet supported.
-== PCB ==
+A Serial header is found at J8. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
+The exchange between the ARM microcontroller and the RTL SoC can be snooped by connecting a logic analyzer to header J9. Square pin is 3.3V, the middle pins are TX from SoC and ARM chip respectively, the pin opposite of Vcc is GND.
+==== Pin-outs ====
+=== Soc UART ===
+  * J8.1: VCC, 3.3V (square pad)
+  * J8.2: TX
+  * J8.3: RX
+  * J8.4: GND
+=== PoE UART ===
+The secondary UART on the SoC is used to communicate with the microcontroller to manage PoE. The communications are accessible from J9, which is in the microcontroller's power domain. Note that the SoC is in an isolated power domain, so avoid connecting the VCC or GND lines together.
+  * J9.1: VCC, 3.3V
+  * J9.2: TX (microcontroller to SoC)
+  * J9.3: RX (SoC to microcontroller)
+  * J9.4: GND
+=== Nuvoton SWD ===
+J10 is an SWD header to program the Nuvoton Chip.
+==== Board details ====
 {{wiki:dgs-1210-10p_board.jpg?200}}
-== Links ==
+===== Firmware =====
+The switch ships with a bootloader based on Realtek's SDK for RTL83xx SoCs and Linux 2.6 based on Realtek's SDK. It has a web interface for all management functions.
+The board identifies as RTL8380M_INTPHY_2FIB_1G_DEMO (Port Count: 10) for the Realtek SDK.
+==== OpenWrt Support ====
+There is complete hardware support in an experimental OpenWrt branch for F1 revision (R1 is in the works). Of the L2 features, port isolation, 4096 VLANs, Local Port Mirroring, EEE are supported. Support to do configuration of PoE+ (including prioritizing power for ports) is possible with [[https://patchwork.ozlabs.org/project/openwrt/patch/20210511152243.1167160-1-john@phrozen.org/|realtek-poe]]. Media change is detected on the SFP cages for fibre optic cables, however after hot-swapping an SFP module, manual setup is needed. There is no support to read the SFP ID/Sensor data via I2C.
+Original features such as cable integrity tests, offloaded remote mirroring and Port-ACLs are not yet supported.
+===== References =====
   * [[https://www.dlink.com/en/products/dgs-1210-10p-10-port-gigabit-smart-managed-poe-switch | Product page ]]
-{{tag>dlink-dgs-1210}}
+{{tag>dlink-dgs-1210}} {{tag>jtag}}