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dgs-1210-10p [2020/09/22 20:21] – Apply common page structure svanheule | dgs-1210-10p [2022/04/25 15:52] (current) – Tag with JTAG svanheule | ||
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- | ====== D-Link DGS-1210-10P ====== | + | ====== D-Link DGS-1210-10P |
- | {{wiki: | + | {{ wiki: |
- | The DGS-1210-10P is a 8 + 2-port Gigabit L2 switch with up to 65 Watts of PoE power on the 8 Gigabit ports. | + | The DGS-1210-10P |
===== Hardware ===== | ===== Hardware ===== | ||
- | 2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules. It has an [[RTL8380M]] SoC with 8 built-in PHYs, and a [[RTL8231]] GPIO extender to control the port LEDs, system LED, a reset button and a mode switch button for the PoE. Both buttons are software controlled. Power is supplied via a 5V 2A barrel connector. | + | * [[rtl838x|RTL8380M]] SoC |
- | The RTL 8380M SoC has 128MB internal RAM. There is 32MB Flash memory (U19). | + | * Macronix MX25L25635F (32 MiB flash) |
- | A Serial header is found at J3. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1. | + | * 128 MiB (256 MiB Nanya NT5CC256M8JQ-EK on R1) RAM |
+ | * [[rtl8231|RTL8231]] GPIO extender to control the port LEDs, system LED, SFP auxiliary signals, a reset button and a mode switch button for the PoE. Both buttons are software controlled. | ||
+ | * Nuvoton M0516LDE ARM microcontroller to service the PoE controller | ||
+ | * Broadcom BCM59121B0KMLG PoE controller | ||
- | PoE is controlled by a Broadcom BCM59121B0KMLG via a Nuvoton ARM microcontroller, | + | 2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules. |
+ | Power is supplied via a 54V 1.6A barrel connector. PoE budget is 65 W with 30 W maximum per port. | ||
+ | |||
+ | A Serial header is found at J8. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1. | ||
+ | |||
+ | The exchange between the ARM microcontroller and the RTL SoC can be snooped by connecting a logic analyzer to header J9. Square pin is 3.3V, the middle pins are TX from SoC and ARM chip respectively, | ||
+ | |||
+ | ==== Pin-outs ==== | ||
+ | |||
+ | === Soc UART === | ||
+ | * J8.1: VCC, 3.3V (square pad) | ||
+ | * J8.2: TX | ||
+ | * J8.3: RX | ||
+ | * J8.4: GND | ||
+ | |||
+ | === PoE UART === | ||
+ | The secondary UART on the SoC is used to communicate with the microcontroller to manage PoE. The communications are accessible from J9, which is in the microcontroller' | ||
+ | |||
+ | * J9.1: VCC, 3.3V | ||
+ | * J9.2: TX (microcontroller to SoC) | ||
+ | * J9.3: RX (SoC to microcontroller) | ||
+ | * J9.4: GND | ||
+ | |||
+ | === Nuvoton SWD === | ||
+ | J10 is an SWD header to program the Nuvoton Chip. | ||
==== Board details ==== | ==== Board details ==== | ||
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The board identifies as RTL8380M_INTPHY_2FIB_1G_DEMO (Port Count: 10) for the Realtek SDK. | The board identifies as RTL8380M_INTPHY_2FIB_1G_DEMO (Port Count: 10) for the Realtek SDK. | ||
- | ==== OpenWRT | + | ==== OpenWrt |
- | There is complete hardware support in an experimental | + | There is complete hardware support in an experimental |
Original features such as cable integrity tests, offloaded remote mirroring and Port-ACLs are not yet supported. | Original features such as cable integrity tests, offloaded remote mirroring and Port-ACLs are not yet supported. | ||
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* [[https:// | * [[https:// | ||
- | {{tag> | + | {{tag> |