Differences

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--- dgs-1210-10p [2021/09/19 18:50] – [D-Link DGS-1210-10P (rev F)] mention R revision which is very similar pfertser
+++ dgs-1210-10p [2022/04/25 15:52] (current) – Tag with JTAG svanheule
@@ Line 7: / Line 7: @@
 ===== Hardware =====
   * [[rtl838x|RTL8380M]] SoC
-  * Macronix MX25L25635F (32MB flash)
+  * Macronix MX25L25635F (32 MiB flash)
-  * (128MB RAM)
+  * 128 MiB (256 MiB Nanya NT5CC256M8JQ-EK on R1) RAM
-  * [[rtl8231|RTL8231]] GPIO extender to control the port LEDs, system LED, a reset button and a mode switch button for the PoE. Both buttons are software controlled.
+  * [[rtl8231|RTL8231]] GPIO extender to control the port LEDs, system LED, SFP auxiliary signals, a reset button and a mode switch button for the PoE. Both buttons are software controlled.
-  * Nuvoton ARM microcontroller
+  * Nuvoton M0516LDE ARM microcontroller to service the PoE controller
   * Broadcom BCM59121B0KMLG PoE controller
 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
-Power is supplied via a 54V 1.6A barrel connector.
+Power is supplied via a 54V 1.6A barrel connector. PoE budget is 65 W with 30 W maximum per port.
-<del>The RTL 8380M SoC has 128MB internal RAM.</del>
+A Serial header is found at J8. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
-A Serial header is found at J3. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
 The exchange between the ARM microcontroller and the RTL SoC can be snooped by connecting a logic analyzer to header J9. Square pin is 3.3V, the middle pins are TX from SoC and ARM chip respectively, the pin opposite of Vcc is GND.
@@ Line 26: / Line 24: @@
 === Soc UART ===
-  * J3.1: VCC, 3.3V (square pad)
+  * J8.1: VCC, 3.3V (square pad)
-  * J3.2: TX
+  * J8.2: TX
-  * J3.3: RX
+  * J8.3: RX
-  * J4.4: GND
+  * J8.4: GND
 === PoE UART ===
@@ Line 51: / Line 49: @@
 ==== OpenWrt Support ====
-There is complete hardware support in an experimental OpenWrt branch. Of the L2 features, port isolation, 4096 VLANs, Local Port Mirroring, EEE are supported. There is support to do a basic configuration of PoE, advanced features such as prioritizing power for ports is not supported so far. Media change is detected on the SFP cages for fibre optic cables, however after hot-swapping an SFP module, manual setup is needed. There is no support to read the SFP ID/Sensor data via I2C.
+There is complete hardware support in an experimental OpenWrt branch for F1 revision (R1 is in the works). Of the L2 features, port isolation, 4096 VLANs, Local Port Mirroring, EEE are supported. Support to do configuration of PoE+ (including prioritizing power for ports) is possible with [[https://patchwork.ozlabs.org/project/openwrt/patch/20210511152243.1167160-1-john@phrozen.org/|realtek-poe]]. Media change is detected on the SFP cages for fibre optic cables, however after hot-swapping an SFP module, manual setup is needed. There is no support to read the SFP ID/Sensor data via I2C.
 Original features such as cable integrity tests, offloaded remote mirroring and Port-ACLs are not yet supported.
@@ Line 58: / Line 56: @@
   * [[https://www.dlink.com/en/products/dgs-1210-10p-10-port-gigabit-smart-managed-poe-switch | Product page ]]
-{{tag>dlink-dgs-1210}}
+{{tag>dlink-dgs-1210}} {{tag>jtag}}