The RTL930x PLL is currently a bit mysterious, but we have working code to calculate the clocks. As can be seen in the clock-tree, there are 3 main PLL's, presumably all feeding of the main 25MHz reference clock.
The CPU PLL can be have 2 sources, either the LX bus (not sure which one, LXB, LX0 …) or the OCP0 PLL. This seems to be handled via the SYS_STATUS register, though unclear is what LX bus and what freq we are talking about. The SDKclock generator cache lock does teach us how this is done in the vendor code.
OCP PLL
The Open Core Protocol (OCP) bus is fed by the OCP-pll to generate the OCP clock. Not much is known of the OCP PLL, but it seems to be called 'PLL0' and its expected value is `0x0001cda9` as per sdk.
The SDK yields as function. $$VCO = \frac{25 \, \mathrm{MHz} \times N4 \times N1}{P}$$ and then the CPU divisor becomes: $$CPUCLK = \frac{VCO}{N2 \times N3}$$
where
- P is prediv in the ctr1 register,
- N1 is ncode_in in the ctr0 register,
- N2 is div2_cpu in the misc register,
- N3 is div3 in the ctr1 register,
- N4 is div4 in the ctrl0 register,
There are also some control registers, that turn on/off certain components.
- ctrl0_sel_prediv to enable/disable the pre-devisor (e.g. 1 = P e.g. P/P e.g. prediv = 1)
- ctrl0_sel_div4 to enable/disable N4 (e.g. N4 = 1)
which can be re-written to be mathematically easier to implement (in code) $$\frac{25 \, \mathrm{MHz} \times N1}{P \times N2 \times N3} \times N4$$
These calculations seem to be defined-ish in the SDK.
Some doubts on those calculations must be in order, as the documentation states that OCP-PLL with a div of 1/2/4 yields the CPU clock. IOW is N3 the CPU-div and the rest the OCP-pll config? What about PLL0 configuration? Not crucial for the OCP-pl (or MEM-pll), as only 1 device is on this bus (though SRAM is supposed to be on the same bus …), what about a more complex device as the switchcore-pll?