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| gs1900-48 [2021/01/20 13:44] – [Board configuration] bkoblitz | gs1900-48 [2023/01/19 16:36] (current) – Serial header pin-out svanheule | ||
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| The GS1900-48 is a 48 + 2-port Gigabit L2 switch with 48 gigabit ports. | The GS1900-48 is a 48 + 2-port Gigabit L2 switch with 48 gigabit ports. | ||
| + | |||
| + | ===== Firmware ===== | ||
| + | It ships with a bootloader based on Realtek' | ||
| + | |||
| + | ==== OpenWRT Support ==== | ||
| + | There is experimental hardware support for the device in OpenWRT. SFP does not work. | ||
| + | |||
| ===== Hardware ====== | ===== Hardware ====== | ||
| Line 9: | Line 16: | ||
| * Macronix MX25l12805D (16MB flash) | * Macronix MX25l12805D (16MB flash) | ||
| * 128MB RAM | * 128MB RAM | ||
| - | * 6 * [[RTL8218B]] external PHY | + | * 6 × [[RTL8218B]] external PHY |
| - | * 2 * [[RTL8231]] GPIO extenders to control the port LEDs, system LED and reset button | + | * 2 × [[RTL8231]] GPIO extenders |
| + | * One configured as shift register | ||
| + | * One configured in MIIM mode (phy address 0x3) for GPIO usage: | ||
| 2 Uplink ports are SFP cages which support 1000 Base-X tmini GBIC modules. | 2 Uplink ports are SFP cages which support 1000 Base-X tmini GBIC modules. | ||
| - | Power is supplied via a 230 volt mains connector. The board has a hard reset switch SW1, which is is not reachable from the outside. J4 provides a 12V RS232 serial connector which is connected through U8 to the 3.3V UART of | + | Power is supplied via a 230 volt mains connector. The board has a hard reset switch SW1, which is is not reachable from the outside. J4 provides a 12V RS232 serial connector |
| the RTL8393. Conversion is done by U8, a SIPEX 3232EC. To connect to the UART, wires can be soldered to R603 and R602. | the RTL8393. Conversion is done by U8, a SIPEX 3232EC. To connect to the UART, wires can be soldered to R603 and R602. | ||
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| {{wiki: | {{wiki: | ||
| - | ===== Firmware ===== | + | ==== JTAG ==== |
| - | It ships with a bootloader based on Realtek' | + | The board has an unpopulated eJTAG header. The SMD resistor configuration is such that the interface is disabled by default. To be able to use the JTAG interface, the following changes need to be made: |
| + | * R171 permanently asserts nTRST. Move R171 (pull-down) to R525 (pull-up) to allow remote assertion of nTRST. | ||
| + | * R48 is unpopulated, | ||
| + | * Add 2×7 pin header, or at least add connections to TDI, TDO, TCK, TMS and (one) GND pins. | ||
| - | ==== OpenWRT Support | + | With these modifications, |
| - | There is experimental hardware support | + | |
| + | < | ||
| + | Info : JTAG tap: auto0.tap tap/device found: 0x00001001 (mfg: 0x000 (< | ||
| + | Info : JTAG tap: auto1.tap tap/device found: 0x00000001 (mfg: 0x000 (< | ||
| + | </ | ||
| + | |||
| + | ==== Hard reset circuit | ||
| + | |||
| + | {{wiki: | ||
| + | |||
| + | Looking at the circuit around the hard reset button (SW1), one can see an RC (debouncing) circuit (R210+C32). R465 is a pull-up, to maintain the de-asserted state of the RC-circuit' | ||
| + | |||
| + | U25 has marking " | ||
| + | |||
| + | The board config reports that GPIO5 on the RTL8231 (U38) can be used to reset the SoC. GPIO5 leads to TP2 on the board, but neither are connected electrically to U25:2 or U25:3, nor to R403 next to the SoC. A bodge wire can be installed to enable runtime reset-by-GPIO. | ||
| ==== Board configuration ==== | ==== Board configuration ==== | ||
| - | The RTL8231 used for the external GPIOs has PHY-ID 3, not 0 as for all known 838x-based models. | ||
| < | < | ||
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| * [[https:// | * [[https:// | ||
| - | {{tag> | + | {{tag> |