Differences

This shows you the differences between two versions of the page.

--- gs1900-48 [2022/04/18 12:38] – Add eJTAG header modification info svanheule
+++ gs1900-48 [2023/01/19 16:36] (current) – Serial header pin-out svanheule
@@ Line 23: / Line 23: @@
 Uplink ports are SFP cages which support 1000 Base-X tmini GBIC modules.
-Power is supplied via a 230 volt mains connector. The board has a hard reset switch SW1, which is is not reachable from the outside. J4 provides a 12V RS232 serial connector which is connected through U8 to the 3.3V UART of
+Power is supplied via a 230 volt mains connector. The board has a hard reset switch SW1, which is is not reachable from the outside. J4 provides a 12V RS232 serial connector (AT/Everex layout) which is connected through U8 to the 3.3V UART of
 the RTL8393. Conversion is done by U8, a SIPEX 3232EC. To connect to the UART, wires can be soldered to R603 and R602.
@@ Line 33: / Line 33: @@
 {{wiki:gs1900-48_board2.jpg?200}}
-=== Hard reset circuit ===
+==== JTAG ====
+The board has an unpopulated eJTAG header. The SMD resistor configuration is such that the interface is disabled by default. To be able to use the JTAG interface, the following changes need to be made:
-{{wiki:zyxel:gs1900-48-gpio-reset-crop.jpg?200}} {{wiki:zyxel:gs1900-48-gpio-reset-bodge.jpg?200}}
-Looking at the circuit around the hard reset button (SW1), one can see an RC (debouncing) circuit (R210+C32). R465 is a pull-up, to maintain the de-asserted state of the RC-circuit's output leading to the SoC (via 0-ohm R403).
-U25 has marking "8AQP" and is most likely some kind of transistor. C666 buffers VCC for pad U25:4, U25:1 (large pad) is connected to GND. U25:3 connects to the SoC's reset line (R403). Pad U25:2 leads to a pull-up resistor (R464 next to U31). It is possible that this is some form of "DC OK" signal, that starts out at GND, but will switch to a high impedance on U25:3 once VCC stabilizes at the required level.
-The board config reports that GPIO5 on the RTL8231 (U38) can be used to reset the SoC. GPIO5 leads to TP2 on the board, but neither are connected electrically to U25:2 or U25:3, nor to R403 next to the SoC. A bodge wire can be installed to enable runtime reset-by-GPIO.
-=== JTAG ===
-The board has an unpopulated eJTAG header. The SMD resistor configuration is such, that the interface is disabled by default. To be able to use the JTAG interface, the following changes need to be made:
   * R171 permanently asserts nTRST. Move R171 (pull-down) to R525 (pull-up) to allow remote assertion of nTRST.
   * R48 is unpopulated, leaving nSRST unconnected. (optional) Add a 0 ohm resistor to complete the connection.
@@ Line 55: / Line 45: @@
 Info : JTAG tap: auto1.tap tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
 </code>
+==== Hard reset circuit ====
+{{wiki:zyxel:gs1900-48-gpio-reset-crop.jpg?200}} {{wiki:zyxel:gs1900-48-gpio-reset-bodge.jpg?200}}
+Looking at the circuit around the hard reset button (SW1), one can see an RC (debouncing) circuit (R210+C32). R465 is a pull-up, to maintain the de-asserted state of the RC-circuit's output leading to the SoC (via 0-ohm R403).
+U25 has marking "8AQP" and is most likely some kind of transistor. C666 buffers VCC for pad U25:4, U25:1 (large pad) is connected to GND. U25:3 connects to the SoC's reset line (R403). Pad U25:2 leads to a pull-up resistor (R464 next to U31). It is possible that this is some form of "DC OK" signal, that starts out at GND, but will switch to a high impedance on U25:3 once VCC stabilizes at the required level.
+The board config reports that GPIO5 on the RTL8231 (U38) can be used to reset the SoC. GPIO5 leads to TP2 on the board, but neither are connected electrically to U25:2 or U25:3, nor to R403 next to the SoC. A bodge wire can be installed to enable runtime reset-by-GPIO.
 ==== Board configuration ====
@@ Line 222: / Line 222: @@
   * [[https://download.zyxel.com/GS1900-48/datasheet/GS1900-48_19.pdf | Product datasheet]]
-{{tag>zyxel-gs1900}}
+{{tag>zyxel-gs1900}} {{tag>jtag}}