Differences

This shows you the differences between two versions of the page.

--- rtl838x [2020/08/26 13:15] – biot
+++ rtl838x [2020/09/18 19:05] (current) – biot
@@ Line 1: / Line 1: @@
-All SoCs in this series have a [[https://en.wikipedia.org/wiki/MIPS_architecture|MIPS]] core.
+=== Realtek RTL838x ===
-^ Chip        ^ Codename     ^ MIPS core       ^ Ports             ^ Comment ^
+The Realtek **RTL8380M**, **RTL8382M** and **RTL8382L** are closely related SoCs.
-| [[8332M]]   | Maple        | 4KEc @ 500MHz   | Up to 24 FE, 4GE  | 8 internal PHYs, 4 Serdes |
-| [[8380M]]   | Maple        | 4KEc @ 500MHz   | 16 GE, 2 SFP      | 8 internal PHYs (8218b), 2 Serdes |
-| [[8382M]]   | Maple        | 4KEc @ 500MHz   | Up to 28 GE       | |
-| [[8382L]]   | Maple        | 4KEc @ 500MHz   | Unmanaged         | 8 internal GE PHYs |
-| [[8351M]]   | Cypress      | 34Kc @ 700MHz   | Up to 24FE, 4GE   | |
-| [[8352M]]   | Cypress      | 34Kc @ 700MHz   | Up to 56 FE       | |
-| [[8353M]]   | Cypress      | 34Kc @ 700MHz   | 48FE, 4 GE        | No emb. PHY, 17.6 GBit switch cap |
-| [[8390M]]   | Cypress      | | | |
-| [[8391M]]   | Cypress      | | | |
-| [[8392M]]   | Cypress      | | | |
-| [[8393M]]   | Cypress      |                 | 52 GE             | No emb PHY 104GBit switch cap |
-=== Links ===
-  * [[https://manualzz.com/doc/31627850/draft-datasheet | Draft datasheet]] for the [[RTL8380M]]/[[RTL8382M]]/[[RTL8382L]].
-  * A series of leaked documents is available in ''libc0607'''s git repo [[https://github.com/libc0607/Realtek_switch_hacking | here]].
+=== Shared characteristics ===
+  * MIPS 4KEc 500MHz CPU
+  * SPI boot flash up to 32MB
+  * 8 gigabit embedded PHYs
+=== Differences ===
+  * The 8380M has an additional 8 PHYs connected via 2 QSGMII ports and 2 SGMII ports, for a total of 18 ports maximum.
+  * The 8382M has 4 QSGMII ports connected to two 8-port PHYs, for 24 ports maximum.
+  * The 8382L has no DDR RAM interface, making it less suited to managed switches.