Both sides previous revision Previous revision Next revision Previous revision zyxel_xgs1210_series [2022/07/28 18:02] – Add XGS1210-12 front picture oliver zyxel_xgs1210_series [2024/05/11 06:23] – Show hidden blocks svanheule
| XGS1010-12 | 8 | 2 (2.5G/1000M/100M) | 2 | | XGS1010-12 | 8 | 2 (2.5G/1000M/100M) | 2 | | XGS1210-12 | 8 | 2 (2.5G/1000M/100M) | 2 | | XGS1210-12 | 8 | 2 (2.5G/1000M/100M) | 2 | === Architecture Overview === The XGS1210 platform makes use of the various SerDeS units on the [[rtl93xx|RTL9302]]. ^ SDS ^ Use ^ | 2 | RTL8218D | | 6 | RTL8226 | | 7 | RTL8226 | | 8 | SFP+ | | 9 | SFP+ | <uml> package "RTL93xx" { node "MIPS 34kc" as mips { [VPE0] [VPE1] } database DDR3 { } database Flash { } mips -- DDR3 mips --> [SwitchCore] : 0x1B000000 mips <-- [SwitchCore] : IRQ23 [SwitchCore] --> [RTL8321]: MDI Bus [SwitchCore] --> [RTL8218D]: MDI Bus [SwitchCore] <--> [RTL8218D]: MII/8 [SwitchCore] --> [RTL8266_0]: MDI Bus [SwitchCore] <--> [RTL8266_1]: MII [SwitchCore] <--> [SFP0] : I2C DATA [SwitchCore] <--> [SFP1] : IC2 DATA mips --> [SPI0] : 0x18001200 mips <-- [SPI0] : IRQ19? [SPI0] <--> Flash: QSPI mips --> [UART0] : 0x1802000 mips <-- [UART0] : IRQ30 } [UART0] --> console RTL8218D --> "lan1-8" RTL8266_0 --> lan9 RTL8266_1 --> lan10 SFP0 --> lan11 SFP1 --> lan12 RTL8321 --> "lan1-8_lime" RTL8321 --> "lan1-8_amber" RTL8321 --> "lan11-12_blue" RTL8321 --> "lan11-12_lime" </uml>
* RTL8218D 8x Gigabit PHY * RTL8218D 8x Gigabit PHY * 2 RTL8226 2.5 Gigabit PHYs * 2 RTL8226 2.5 Gigabit PHYs * reset button (XGS1210-12 only!) * reset button (XGS1210-12 only!) [[https://tech.alpsalpine.com/e/products/detail/SKRTLAE010/|ALPS]] {{ :skrt.pdf |datasheet}} 2 Uplink ports are SFP+ cages which support 10GBit Base-X mini GBIC modules. 2 Uplink ports are SFP+ cages which support 10GBit Base-X mini GBIC modules.
{{wiki:zyxel:zyxel_xgs1210-12.png?200}} {{wiki:zyxel:zyxel_xgs1210-12.png?200}} {{:zyxel_xgs1010-12_back.jpg?200}} {{:zyxel_xgs1010-12_back.jpg?200}} {{::zyxel_xgs1010_strapping_pins.jpg?200|}} {{:xgs-12xx_sfp_traces.png?400|}} {{:xgs-12xx_traces.png?400|}} Close up of the strapping pins match what we get from peripherial address **0xb8000100**: __0x0080200__ __0b1000000001000000000__. It doesn't tell us what is what however, when looking at [[The struct definition|https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/openwrt-dev/loader/u-boot-2011.12/arch/otto40/plr/src/platform/9300/register_map.h#L346]] or the datasheet: {{::screenshot_from_2022-08-15_17-12-29.png?400|}} ==== XGS1010-12 ==== ==== XGS1010-12 ====
=== OEM bootlog === === OEM bootlog === ++++ Bootlog | <code> <code> U-Boot 2011.12.(TRUNK_CURRENT)-svn99721 (Oct 24 2019 - 09:15:40) U-Boot 2011.12.(TRUNK_CURRENT)-svn99721 (Oct 24 2019 - 09:15:40)
RTK.0> RTK.0> </code> </code> ++++ ==== OEM tech-support ==== ==== OEM tech-support ==== <code> RTK.0> sys dump hwp all Profile Information (C00A86D8): Profile-Name: RTL9302B_8218D_2x8226_2xGE Profile-ID: 9300022 Profile-ID-Type: 0 CPU Type: Embedded SW Desc IDX: 0 Slave Interrupt Pin: 255 Chip count: 1 Cascade Mode: No unit 0, 9302(1) (cpu) swcore support: 1 swcore-CPU Interface(1:normal, 2:SPI, 3: PCIe): 1 nic support: 1 port count:13 macId: 0, 1, 2, 3, 4, 5, 6, 7,24,25,26,27,28, CpuMacId: 28 (attr) Ether cnt:12, macId(m/M): 0/27 msk:0x0f0000ff 0x00000000 (A) Uplink cnt: 4, macId(m/M):24/27 msk:0x0f000000 0x00000000 (A) GE cnt: 8, macId(m/M): 0/ 7 msk:0x000000ff 0x00000000 (E) 2_5GE cnt: 2, macId(m/M): 0/25 msk:0x03000000 0x00000000 (E) XGE cnt: 2, macId(m/M):26/27 msk:0x0c000000 0x00000000 (E) Copper cnt:10, macId(m/M): 0/25 msk:0x030000ff 0x00000000 (M) Serdes cnt: 2, macId(m/M):26/27 msk:0x0c000000 0x00000000 (M) port: 0, phyIdx0 port: 1, phyIdx0 port: 2, phyIdx0 port: 3, phyIdx0 port: 4, phyIdx0 port: 5, phyIdx0 port: 6, phyIdx0 port: 7, phyIdx0 port:24, phyIdx1 port:25, phyIdx2 port:26, phyIdx255 port:27, phyIdx255 port:28, phyIdx255 PHY Count:3 type:12(8218D ) port:8 baseMac:0 type:19(RTL8226 ) port:1 baseMac:24 type:19(RTL8226 ) port:1 baseMac:25 PHY[0]: chipID 12, baseMacId 0, phy_max 8 PHY[1]: chipID 19, baseMacId 24, phy_max 1 PHY[2]: chipID 19, baseMacId 25, phy_max 1 unitMapStruct[0].pUnitInfo:86c90014,parsed_info=86c90000,swDescp=c00a8724 unitMapStruct[1].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[2].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[3].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[4].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[5].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[6].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[7].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[8].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[9].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[10].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[11].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[12].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[13].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[14].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 unitMapStruct[15].pUnitInfo:c00bbacc,parsed_info=0,swDescp=0 (&parsedInfoEmpty.unitInfo[EMPTY]=c00bbacc) info->hwp=RTL9302B_8218D_2x8226_2xGE(c00a86d8) info->hwp_localUnitCnt=1 info->hwp_embeddedCpuUnitId=0 info->hwp_cascade_mode=0 info->hwp_cascadeSlaveUnitID=0 info->hwp->swDescp[0]=c00a8724 info->hwp->swDescp[1]=0 info->hwp->swDescp[2]=0 info->unitInfo[0].hwp_chip_id=93021000 info->unitInfo[0].hwp_chip_revision=1 info->unitInfo[0].hwp_chip_family_id=93000000 info->unitInfo[0].hwp_maxMacId=28 info->unitInfo[0].hwp_minMacId=0 info->unitInfo[0].hwp_macID2PortDescp: p[0]=c00a8738,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=1,eth=2,medi=1, p[1]=c00a8748,mac_id=1,phyIdx=0,sdsIdx=0,smi=0,phy_addr=1,attr=1,eth=2,medi=1, p[2]=c00a8758,mac_id=2,phyIdx=0,sdsIdx=0,smi=0,phy_addr=2,attr=1,eth=2,medi=1, p[3]=c00a8768,mac_id=3,phyIdx=0,sdsIdx=0,smi=0,phy_addr=3,attr=1,eth=2,medi=1, p[4]=c00a8778,mac_id=4,phyIdx=0,sdsIdx=0,smi=0,phy_addr=4,attr=1,eth=2,medi=1, p[5]=c00a8788,mac_id=5,phyIdx=0,sdsIdx=0,smi=0,phy_addr=5,attr=1,eth=2,medi=1, p[6]=c00a8798,mac_id=6,phyIdx=0,sdsIdx=0,smi=0,phy_addr=6,attr=1,eth=2,medi=1, p[7]=c00a87a8,mac_id=7,phyIdx=0,sdsIdx=0,smi=0,phy_addr=7,attr=1,eth=2,medi=1, p[8]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[9]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[10]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[11]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[12]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[13]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[14]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[15]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[16]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[17]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[18]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[19]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[20]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[21]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[22]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[23]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[24]=c00a87b8,mac_id=24,phyIdx=1,sdsIdx=1,smi=1,phy_addr=8,attr=3,eth=4,medi=1, p[25]=c00a87c8,mac_id=25,phyIdx=2,sdsIdx=2,smi=2,phy_addr=9,attr=3,eth=4,medi=1, p[26]=c00a87d8,mac_id=26,phyIdx=255,sdsIdx=3,smi=255,phy_addr=255,attr=3,eth=8,medi=8, p[27]=c00a87e8,mac_id=27,phyIdx=255,sdsIdx=4,smi=255,phy_addr=255,attr=3,eth=8,medi=8, p[28]=c00a87f8,mac_id=28,phyIdx=255,sdsIdx=255,smi=255,phy_addr=255,attr=8,eth=255,medi=255, p[29]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[30]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[31]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[32]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[33]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[34]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[35]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[36]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[37]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[38]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[39]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[40]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[41]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[42]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[43]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[44]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[45]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[46]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[47]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[48]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[49]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[50]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[51]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[52]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[53]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[54]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[55]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[56]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[57]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[58]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[59]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[60]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[61]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[62]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, p[63]=c00be0fc,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0, info->unitInfo[0].hwp_macID2SerdesID: p[0]=2,p[1]=2,p[2]=2,p[3]=2,p[4]=2,p[5]=2,p[6]=2,p[7]=2,p[8]=255,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=255,p[21]=255,p[22]=255,p[23]=255,p[24]=6,p[25]=7,p[26]=8,p[27]=9,p[28]=255,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255, info->unitInfo[0].hwp_portCpuMacId=28 Ether : count=12, max=27, min=0 Uplink : count=4, max=27, min=24 Cascade: count=0, max=0, min=64 Fe : count=0, max=0, min=64 Ge : count=8, max=7, min=0 Xge : count=2, max=27, min=26 SXge : count=0, max=0, min=64 Copper : count=10, max=25, min=0 Fiber : count=0, max=0, min=64 Combo : count=0, max=0, min=64 Serdes : count=2, max=27, min=26 info->unitInfo[0].hwp_sdsID2phyType: SDS 2 PHY:12 SDS 6 PHY:19 SDS 7 PHY:19 SDS 8 PHY:20 SDS 9 PHY:20 info->unitInfo[0].hwp_sdsID2MacID: s[2]=0,s[6]=24,s[7]=25,s[8]=26,s[9]=27, info->unitInfo[0].hwp_attriPortMask: attr[0]=f0000ff attr[0]=0 attr[1]=f000000 attr[1]=0 attr[2]=0 attr[2]=0 attr[3]=10000000 attr[3]=0 attr[4]=0 attr[4]=0 info->unitInfo[0].hwp_ethTypePortMask: eth[0]=0 eth[0]=0 eth[1]=ff eth[1]=0 eth[2]=3000000 eth[2]=0 eth[3]=c000000 eth[3]=0 eth[4]=0 eth[4]=0 info->unitInfo[0].hwp_mediumPortMask: med[0]=30000ff med[0]=0 med[1]=0 med[1]=0 med[2]=0 med[2]=0 med[3]=c000000 med[3]=0 info->unitInfo[0].hwp_allPortMask=1f0000ff info->unitInfo[0].hwp_allPortMask=0 info->unitInfo[0].hwp_macID2phyAddr: p[0]=0,p[1]=1,p[2]=2,p[3]=3,p[4]=4,p[5]=5,p[6]=6,p[7]=7,p[8]=255,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=255,p[21]=255,p[22]=255,p[23]=255,p[24]=8,p[25]=9,p[26]=255,p[27]=255,p[28]=255,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255, info->unitInfo[0].hwp_macID2phyType: p[0]=12,p[1]=12,p[2]=12,p[3]=12,p[4]=12,p[5]=12,p[6]=12,p[7]=12,p[8]=27,p[9]=27,p[10]=27,p[11]=27,p[12]=27,p[13]=27,p[14]=27,p[15]=27,p[16]=27,p[17]=27,p[18]=27,p[19]=27,p[20]=27,p[21]=27,p[22]=27,p[23]=27,p[24]=19,p[25]=19,p[26]=20,p[27]=20,p[28]=20,p[29]=27,p[30]=27,p[31]=27,p[32]=27,p[33]=27,p[34]=27,p[35]=27,p[36]=27,p[37]=27,p[38]=27,p[39]=27,p[40]=27,p[41]=27,p[42]=27,p[43]=27,p[44]=27,p[45]=27,p[46]=27,p[47]=27,p[48]=27,p[49]=27,p[50]=27,p[51]=27,p[52]=27,p[53]=27,p[54]=27,p[55]=27,p[56]=27,p[57]=27,p[58]=27,p[59]=27,p[60]=27,p[61]=27,p[62]=27,p[63]=27, info->unitInfo[0].hwp_sdsID2SerdesDescp: sds[0]=c00be0f8,sds[1]=c00be0f8,sds[2]=c00a8b39,sds[3]=c00be0f8,sds[4]=c00be0f8,sds[5]=c00be0f8,sds[6]=c00a8b3b,sds[7]=c00a8b3d,sds[8]=c00a8b3f,sds[9]=c00a8b41,sds[10]=c00be0f8,sds[11]=c00be0f8,sds[12]=c00be0f8,sds[13]=c00be0f8,sds[14]=c00be0f8,sds[15]=c00be0f8,sds[16]=c00be0f8,sds[17]=c00be0f8,sds[18]=c00be0f8,sds[19]=c00be0f8,sds[20]=c00be0f8,sds[21]=c00be0f8,sds[22]=c00be0f8,sds[23]=c00be0f8, info->unitInfo[0].hwp_phyBaseMacID: p[0]=0,p[1]=0,p[2]=0,p[3]=0,p[4]=0,p[5]=0,p[6]=0,p[7]=0,p[8]=255,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=255,p[21]=255,p[22]=255,p[23]=255,p[24]=24,p[25]=25,p[26]=26,p[27]=27,p[28]=28,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255, info->unitInfo[0].hwp_ledNum: p[0]=2,p[1]=2,p[2]=2,p[3]=2,p[4]=2,p[5]=2,p[6]=2,p[7]=2,p[8]=0,p[9]=0,p[10]=0,p[11]=0,p[12]=0,p[13]=0,p[14]=0,p[15]=0,p[16]=0,p[17]=0,p[18]=0,p[19]=0,p[20]=0,p[21]=0,p[22]=0,p[23]=0,p[24]=4,p[25]=4,p[26]=2,p[27]=2,p[28]=255,p[29]=0,p[30]=0,p[31]=0,p[32]=0,p[33]=0,p[34]=0,p[35]=0,p[36]=0,p[37]=0,p[38]=0,p[39]=0,p[40]=0,p[41]=0,p[42]=0,p[43]=0,p[44]=0,p[45]=0,p[46]=0,p[47]=0,p[48]=0,p[49]=0,p[50]=0,p[51]=0,p[52]=0,p[53]=0,p[54]=0,p[55]=0,p[56]=0,p[57]=0,p[58]=0,p[59]=0,p[60]=0,p[61]=0,p[62]=0,p[63]=0, info->unitInfo[0].hwp_multiSdsPortSdsmask: info->unitInfo[0].hwp_multiSdsBaseSds: info->unitInfo[0].hwp_macID2SCDescp: info->unitInfo[0].hwp_scBaseMacID: info->unitInfo[0].swDescp=c00a8724 info->unitInfo[0].parsed_info=86c90000 </code> By tftpbooting the XGS1210-12 `.bix` file, we get into the Zylinx shell, which while restrictive, allows us to do `show tech-support`. By tftpbooting the XGS1210-12 `.bix` file, we get into the Zylinx shell, which while restrictive, allows us to do `show tech-support`. === Board GPIO === === Board GPIO ===
Device Pin Direction Default Current Purpose Device Pin Direction Default Current Purpose ------- ---- ---------- -------- -------- -------- ------- ---- ---------- -------- -------- -------- INT 0 OUT 0 0 SYSTEM-LED INT 0 OUT 0 0 SYSTEM-LED INT 6 IN 1 1 HW_VER_BIT0 INT 1 N/A Not Connected INT 7 IN 1 0 HW_VER_BIT1 INT 2 N/A Not Connected INT 8 SFP0/SFP1: SCK SPI 3 N/A Goes to unpopluated U23 (SPI_CLK) INT 9 SFP0 : SDA SPI 4 N/A Goes to unpopluated U23 (SPI_MISO) INT 10 SFP1 : SDA SPI 5 N/A Goes to unpopluated U23 (SPI_MOSI) INT 11 OUT 0 0 SFP0: TX_DIS_FX_0 INT 6 IN 0 0 Permanently Pulled down, likely to indicate presence of U23 INT 12 IN 0 0 SFP0: MOD-DEF0 INT 7 IN 1 1 Permanently Pulled up, likely to indicate presence of ...? INT 13 IN 0 0 SFP0: LOS I2C 8 OUT Shared SFP clock ( SFP0/SFP1: SCK) Pull-up near SFP0 INT 14 IN 0 0 I2C 9 I/O SDA0 : (SFP0_SDA) Pull-up near SFP0 INT 15 OUT 0 0 SPF1 : TX_DIS_FX_1 I2C 10 I/O SDA1 : (SFP1_SDA) Pull-up near SFP1 INT 16 IN 0 1 SFP1: MOD-DEF0 INT 11 OUT 0 0 Transmit Disable ( SFP0: TX_DIS_FX) Pull-up near SFP0 INT 17 IN 0 1 SFP1: LOS INT 12 IN 0 0 Absent detection ( SFP0: MOD-DEF0) Pull-up near SFP0 INT 20 IN 0 1 INT 13 IN 0 0 Los of Signal ( SFP0: LOS) Pull-up near SFP0 (pull down NP option) INT 21 OUT 1 1 Reset_PHY INT 14 IN 0 0 Transmit Fault (SFP0: TX_FAULT) Pull-up near SFP0 INT 22 IN 1 1 Reset_Button INT 15 OUT 0 0 Transmit Disable (SFP1 : TX_DIS_FX) Pull-up near SFP1 INT 16 IN 0 0 Absent detection ( SFP1: MOD-DEF0) Pull-up near SFP1 INT 17 IN 0 0 Los of Signal ( SFP1: LOS) Pull-up near SFP1 (pull down NP option) INT 18 IN 0 0 Permanently pulled down? Trace not found ... INT 19 IN 0 0 Permanently pulled down? Trace not found ... INT 20 OUT 0 0 Goes to U10? INT 21 IN 0 0 Transmit Fault (SFP1: TX_FAULT) Pull-up near SFP1 INT 22 OUT 1 1 Reset_PHY? INT 23 IN Reset Button </code> </code> Note, that RS0/RS1 for both SFP's have permanent pull-ups, but also have the pull-down option. Not connected/lost traces can still exist on an internal layer (Reset for example). == USB == While this switch has no USB ports, the USB pins appear to be on TP2 and TP3 on the bottom (to be confirmed) {{ :tech-support.rtf | Full tech-support output}} {{ :tech-support.rtf | Full tech-support output}}
mtd6: 00680000 00001000 "RUNTIME2" mtd6: 00680000 00001000 "RUNTIME2" </code> </code> === OEM U-Boot Self-test failure === <code> ============= Factory Test Begin ============= HTP log info get: htpModeIf=1, htpBreakIf=0, hour=20, entry=12800, round=808859448 ! HTP Test log full! ============= Factory Test End ! ============= </code> The OEM bootloader (U-Boot 2011.12.(TRUNK_CURRENT)-svn99721 (Oct 24 2019 - 09:15:40)) runs a [[https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/xgs1010/loader/u-boot-2011.12/common/main.c#L223|self-check]] upon startup. This check byte is in the middle of the flash, [[https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/xgs1010/loader/u-boot-2011.12/board/Realtek/switch/sdk/system/uboot/cmd/uboot_func.c#L61|stored at address `0x810000` (just beyond the 8MiB marker) on the XGS1010-12]]. With the recently new introduced mtd-concat, we can however define two regions and concatate those logically in Linux. The upside is, unless Zyxel recompiled their firmware (unnecessary work for them, but possible), using a smaller flash-chip would be less-likely. As an alternative, the XGS1210-12 U-Boot binary can be flashed, which turns the XGS1010-12 'more' into a XGS1210-12, [[https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/xgs1210/sdk/system/uboot/cmd/uboot_func.c#L62|which puts this self-check at the end of the flash]].
===== OpenWRT Bootlog ==== ===== OpenWRT Bootlog ==== ++++ Full OpenWRT Bootlog | <code> <code> Board: RTL9300 CPU:800MHz LX:175MHz DDR:600MHz Board: RTL9300 CPU:800MHz LX:175MHz DDR:600MHz
[ 0.020076] printk: bootconsole [early0] disabled [ 0.020076] printk: bootconsole [early0] disabled </code> </code> ++++ ==== OpenWrt Support ==== ==== OpenWrt Support ====