| S0_REG_BIAS_PICORE_KP |
2046 |
2 |
|
| S0_REG_INT_INIT |
2032 |
14 |
|
| S0_REG_BIAS_PICORE_KI |
2030 |
2 |
|
| S0_REG_BIAS_STR |
2027 |
3 |
|
| S0_REG_ACC2_MANUAL |
2026 |
1 |
|
| S0_REG_ACC2_PERIOD |
2016 |
10 |
|
| S0_REG_BITSEL |
2015 |
1 |
|
| S0_REG_EQ_LO_BND2 |
2010 |
5 |
|
| S0_REG_EQ_LO_BND1 |
2005 |
5 |
|
| S0_REG_EQ_LO_BND0 |
2000 |
5 |
|
| S0_REG_CDR_RESET_SEL |
1999 |
1 |
|
| S0_REG_CLKLA_AMP |
1996 |
3 |
|
| S0_REG_CK25MO_E4 |
1995 |
1 |
|
| S0_REG_CK25MO_EN |
1994 |
1 |
|
| S0_REG_EQ_UP_BND3 |
1989 |
5 |
|
| S0_REG_EQ_UP_BND2 |
1984 |
5 |
|
| S0_REG_BIAS_PIFINE_KI |
1982 |
2 |
|
| S0_REG_EQ_PERIOD1 |
1975 |
7 |
|
| S0_REG_EQ_PERIOD0 |
1968 |
7 |
|
| S0_REG_RELOAD_EN |
1967 |
1 |
|
| S0_REG_EQ_UP_BND1 |
1962 |
5 |
|
| S0_REG_EQ_UP_BND0 |
1957 |
5 |
|
| S0_REG_EQ_LO_BND3 |
1952 |
5 |
|
| S0_REG_ST2_INIT_1 |
1936 |
16 |
|
| S0_REG_BIAS_PIFINE_KP |
1934 |
2 |
|
| S0_REG_EQ_PERIOD3 |
1927 |
7 |
|
| S0_REG_EQ_PERIOD2 |
1920 |
7 |
|
| S0_REG_LPFEN_MANUAL |
1919 |
1 |
|
| S0_REG_OCHOLD |
1918 |
1 |
|
| S0_REG_OC_SLICER |
1917 |
1 |
|
| S0_REG_OC_SELREG |
1916 |
1 |
|
| S0_REG_OC_GAIN |
1913 |
3 |
|
| S0_REG_EN2_INIT_1 |
1909 |
4 |
|
| S0_REG_ST_M_VALUE |
1904 |
5 |
|
| S0_REG_ST_M_VALUE_1 |
1888 |
16 |
|
| S0_REG_BYPASS_SDM_INT |
1887 |
1 |
|
| S0_REG_TIMER_EQ3 |
1882 |
5 |
|
| S0_REG_TIMER_EQ2 |
1877 |
5 |
|
| S0_REG_TIMER_EQ1 |
1872 |
5 |
|
| S0_REG_RX_OEB_CKPIO13 |
1871 |
1 |
|
| S0_REG_TIMER_EQ0 |
1866 |
5 |
|
| S0_REG_TIMER_DCCAL |
1861 |
5 |
|
| S0_REG_TIMER_BER |
1856 |
5 |
|
| S0_REG_EQ_SLICER3 |
1855 |
1 |
|
| S0_REG_EQ_SLICER2 |
1854 |
1 |
|
| S0_REG_EQ_SLICER1 |
1853 |
1 |
|
| S0_REG_EQ_SLICER0 |
1852 |
1 |
|
| S0_REG_TIMER_EQHOLD3 |
1846 |
6 |
|
| S0_REG_TIMER_EQHOLD2 |
1840 |
6 |
|
| S0_REG_EQHOLD |
1836 |
4 |
|
| S0_REG_TIMER_EQHOLD1 |
1830 |
6 |
|
| S0_REG_TIMER_EQHOLD0 |
1824 |
6 |
|
| S0_REG_CK25MO_E32 |
1822 |
2 |
|
| S0_REG_RX_DBG_SEL |
1820 |
2 |
|
| S0_REG_EQ_GAIN3 |
1817 |
3 |
|
| S0_REG_EQ_GAIN2 |
1814 |
3 |
|
| S0_REG_EQ_GAIN1 |
1811 |
3 |
|
| S0_REG_EQ_GAIN0 |
1808 |
3 |
|
| S0_REG_OFFSET_ADJR |
1804 |
4 |
|
| S0_REG_OOBS_SEN_VAL |
1799 |
5 |
|
| S0_REG_OC_PERIOD |
1792 |
7 |
|
| S0_REG_VSEL_LREG |
1789 |
3 |
|
| S0_REG_LCVCO_TR_3_ |
1788 |
1 |
|
| S0_REG_LCVCO_TR_2_ |
1787 |
1 |
|
| S0_REG_LCVCO_TR_1_ |
1786 |
1 |
|
| S0_REG_LCVCO_TR_0_ |
1785 |
1 |
|
| S0_REG_INIT_TIME |
1782 |
3 |
|
| S0_REG_CP_TIME |
1779 |
3 |
|
| S0_REG_CALIB_TIME |
1776 |
3 |
|
| S0_REG_OFFSET_RANGE |
1774 |
2 |
|
| S0_REG_OFFSET_AUTOK |
1773 |
1 |
|
| S0_REG_EN_KOFFSET |
1772 |
1 |
|
| S0_REG_TESTOUT_SEL_1 |
1770 |
2 |
|
| S0_REG_TESTOUT_SEL |
1768 |
2 |
|
| S0_REG_SQU_TRI |
1767 |
1 |
|
| S0_REG_RX_IDLE_SPD |
1766 |
1 |
|
| S0_REG_RX_SEL_RXIDLE |
1765 |
1 |
|
| S0_REG_RX_EN_TEST |
1764 |
1 |
|
| S0_REG_RX_FORCERUN |
1763 |
1 |
|
| S0_REG_RX_DATA_EN_SEL |
1762 |
1 |
|
| S0_REG_RX_CLKWR_EN_SEL |
1761 |
1 |
|
| S0_REG_RESET_MANUAL |
1760 |
1 |
|
| S0_REG_TX_SWING25 |
1759 |
1 |
|
| S0_REG_TX_VCM_RES |
1758 |
1 |
|
| S0_REG_TX_EN_TEST |
1757 |
1 |
|
| S0_REG_ZTUNE |
1756 |
1 |
|
| S0_REG_ZTEST |
1755 |
1 |
|
| S0_REG_TX_SEL_CKRD_DUTY |
1754 |
1 |
|
| S0_REG_Z0_PAUTO_K |
1753 |
1 |
|
| S0_REG_Z0_PADJR |
1749 |
4 |
|
| S0_REG_Z0_NAUTO_K |
1748 |
1 |
|
| S0_REG_Z0_NADJR |
1744 |
4 |
|
| S0_REG_CMU_SEL_WDCK |
1743 |
1 |
|
| S0_REG_CMU_EN_WD |
1742 |
1 |
|
| S0_REG_IB_CENTER_FILTER |
1741 |
1 |
|
| S0_REG_IB_FILTER |
1740 |
1 |
|
| S0_REG_SINGVCO |
1739 |
1 |
|
| S0_REG_LCBIAS_LPF_EN |
1738 |
1 |
|
| S0_REG_ISTANK_SEL_LS_1_ |
1737 |
1 |
|
| S0_REG_ISTANK_SEL_LS_0_ |
1736 |
1 |
|
| S0_REG_FLD_DSEL |
1735 |
1 |
|
| S0_REG_CMU_VCP_SEL |
1734 |
1 |
|
| S0_REG_CMU_AUTO_K |
1733 |
1 |
|
| S0_REG_CLKRDY |
1731 |
2 |
|
| S0_REG_ADP_TIME |
1728 |
3 |
|
| S0_DUMMY_RG1514_3116 |
1712 |
16 |
|
| S0_REG_BG |
1710 |
2 |
|
| S0_REG_TX_SWING |
1708 |
2 |
|
| S0_REG_IBRXSEL |
1706 |
2 |
|
| S0_REG_IBTXSEL |
1704 |
2 |
|
| S0_REG_DATA_TRANS |
1700 |
4 |
|
| S0_REG_EN_M_VALUE |
1696 |
4 |
|
| S0_REG_FILTER_OUT0_TG |
1691 |
5 |
|
| S0_REG_EQ_SELREG_TG |
1687 |
4 |
|
| S0_REG_EQ_IN_TG |
1680 |
7 |
|
| S0_REG_FILTER_OUT0_XSG |
1675 |
5 |
|
| S0_REG_EQ_SELREG_XSG |
1671 |
4 |
|
| S0_REG_EQ_IN_XSG |
1664 |
7 |
|
| S0_REG_RX_EQ_BOOST_DC_TG |
1663 |
1 |
|
| S0_REG_FILTER_OUT3_TG |
1658 |
5 |
|
| S0_REG_FILTER_OUT2_TG |
1653 |
5 |
|
| S0_REG_FILTER_OUT1_TG |
1648 |
5 |
|
| S0_REG_RX_EQ_BOOST_DC_XSG |
1647 |
1 |
|
| S0_REG_FILTER_OUT3_XSG |
1642 |
5 |
|
| S0_REG_FILTER_OUT2_XSG |
1637 |
5 |
|
| S0_REG_FILTER_OUT1_XSG |
1632 |
5 |
|
| S0_REG_ST2_M_VALUE_1_TG |
1616 |
16 |
|
| S0_REG_ST2_M_VALUE_1_XSG |
1600 |
16 |
|
| S0_REG_CLKLA_EN_TG |
1599 |
1 |
|
| S0_REG_RSEL_TG |
1597 |
2 |
|
| S0_REG_KI_TG |
1594 |
3 |
|
| S0_REG_KD_TG |
1593 |
1 |
|
| S0_REG_KP2_TG |
1590 |
3 |
|
| S0_REG_KP1_TG |
1588 |
2 |
|
| S0_REG_KP1_1_TG |
1584 |
4 |
|
| S0_REG_CLKLA_EN_XSG |
1583 |
1 |
|
| S0_REG_RSEL_XSG |
1581 |
2 |
|
| S0_REG_KI_XSG |
1578 |
3 |
|
| S0_REG_KD_XSG |
1577 |
1 |
|
| S0_REG_KP2_XSG |
1574 |
3 |
|
| S0_REG_KP1_XSG |
1572 |
2 |
|
| S0_REG_KP1_1_XSG |
1568 |
4 |
|
| S0_REG_PR1_KP_RSEL_TG |
1566 |
2 |
|
| S0_REG_PR2_KI_RSEL_TG |
1564 |
2 |
|
| S0_REG_OOBS_VCM_TG |
1562 |
2 |
|
| S0_REG_PI_HOLD_TG |
1561 |
1 |
|
| S0_REG_PI2_HOLD_1_TG |
1560 |
1 |
|
| S0_REG_PI_HOLD_1_TG |
1559 |
1 |
|
| S0_REG_OFFSET_SR_TG |
1557 |
2 |
|
| S0_REG_OFFSET_IH_TG |
1555 |
2 |
|
| S0_REG_OOBS_SEL_TG |
1554 |
1 |
|
| S0_REG_OOBS_FREQ_SEL_TG |
1553 |
1 |
|
| S0_REG_PI_IBX_SEL_TG |
1552 |
1 |
|
| S0_REG_PR1_KP_RSEL_XSG |
1550 |
2 |
|
| S0_REG_PR2_KI_RSEL_XSG |
1548 |
2 |
|
| S0_REG_OOBS_VCM_XSG |
1546 |
2 |
|
| S0_REG_PI_HOLD_XSG |
1545 |
1 |
|
| S0_REG_PI2_HOLD_1_XSG |
1544 |
1 |
|
| S0_REG_PI_HOLD_1_XSG |
1543 |
1 |
|
| S0_REG_OFFSET_SR_XSG |
1541 |
2 |
|
| S0_REG_OFFSET_IH_XSG |
1539 |
2 |
|
| S0_REG_OOBS_SEL_XSG |
1538 |
1 |
|
| S0_REG_OOBS_FREQ_SEL_XSG |
1537 |
1 |
|
| S0_REG_PI_IBX_SEL_XSG |
1536 |
1 |
|
| S0_REG_RX_EN_SELF_TG |
1535 |
1 |
|
| S0_REG_OOBS_RXIDLE_MANUAL_TG |
1534 |
1 |
|
| S0_REG_OOBS_CKSEL_TG |
1533 |
1 |
|
| S0_REG_PI2_M_MODE_1_TG |
1532 |
1 |
|
| S0_REG_PI_M_MODE_1_TG |
1531 |
1 |
|
| S0_REG_PI_M_MODE_TG |
1530 |
1 |
|
| S0_REG_EN2_M_VALUE_1_TG |
1526 |
4 |
|
| S0_REG_OOBS_NSQDLY_SEL_TG |
1525 |
1 |
|
| S0_REG_OOBS_SWEN_TG |
1524 |
1 |
|
| S0_REG_RSSI_SEN_TG |
1522 |
2 |
|
| S0_REG_OOBS_CALI_TG |
1520 |
2 |
|
| S0_REG_RX_EN_SELF_XSG |
1519 |
1 |
|
| S0_REG_OOBS_RXIDLE_MANUAL_XSG |
1518 |
1 |
|
| S0_REG_OOBS_CKSEL_XSG |
1517 |
1 |
|
| S0_REG_PI2_M_MODE_1_XSG |
1516 |
1 |
|
| S0_REG_PI_M_MODE_1_XSG |
1515 |
1 |
|
| S0_REG_PI_M_MODE_XSG |
1514 |
1 |
|
| S0_REG_EN2_M_VALUE_1_XSG |
1510 |
4 |
|
| S0_REG_OOBS_NSQDLY_SEL_XSG |
1509 |
1 |
|
| S0_REG_OOBS_SWEN_XSG |
1508 |
1 |
|
| S0_REG_RSSI_SEN_XSG |
1506 |
2 |
|
| S0_REG_OOBS_CALI_XSG |
1504 |
2 |
|
| S0_REG_DIVIDE_NUM_TG |
1498 |
6 |
|
| S0_REG_LOCK_DN_LIMIT_TG |
1488 |
10 |
|
| S0_REG_DIVIDE_NUM_XSG |
1482 |
6 |
|
| S0_REG_LOCK_DN_LIMIT_XSG |
1472 |
10 |
|
| S0_REG_LCVCO_HSMODE_TG |
1471 |
1 |
|
| S0_REG_CMU_LOOP_DIVN_TG |
1466 |
5 |
|
| S0_REG_LOCK_UP_LIMIT_TG |
1456 |
10 |
|
| S0_REG_LCVCO_HSMODE_XSG |
1455 |
1 |
|
| S0_REG_CMU_LOOP_DIVN_XSG |
1450 |
5 |
|
| S0_REG_LOCK_UP_LIMIT_XSG |
1440 |
10 |
|
| S0_REG_ISTANK_SEL_HS_TG_1 |
1439 |
1 |
|
| S0_REG_ISTANK_SEL_HS_TG_0 |
1438 |
1 |
|
| S0_REG_CMU_SEL_CP_TG |
1436 |
2 |
|
| S0_REG_CMU_SELPREDIV_TG |
1434 |
2 |
|
| S0_REG_CMU_LOOP_DIV4_TG |
1432 |
2 |
|
| S0_REG_CMU_ICP_SEL_TG |
1428 |
4 |
|
| S0_REG_CMU_SEL_R_TG_3 |
1427 |
1 |
|
| S0_REG_CMU_SEL_R_TG_2_0 |
1424 |
3 |
|
| S0_REG_ISTANK_SEL_HS_XSG_1 |
1423 |
1 |
|
| S0_REG_ISTANK_SEL_HS_XSG_0 |
1422 |
1 |
|
| S0_REG_CMU_SEL_CP_XSG |
1420 |
2 |
|
| S0_REG_CMU_SELPREDIV_XSG |
1418 |
2 |
|
| S0_REG_CMU_LOOP_DIV4_XSG |
1416 |
2 |
|
| S0_REG_CMU_ICP_SEL_XSG |
1412 |
4 |
|
| S0_REG_CMU_SEL_R_XSG_3 |
1411 |
1 |
|
| S0_REG_CMU_SEL_R_XSG_2_0 |
1408 |
3 |
|
| S0_REG_TXLA_IBXSEL_TG |
1407 |
1 |
|
| S0_REG_TX_D2_AMP_TG |
1402 |
5 |
|
| S0_REG_TX_D1_AMP_TG |
1397 |
5 |
|
| S0_REG_TX_D0_AMP_TG |
1392 |
5 |
|
| S0_REG_TXLA_IBXSEL_XSG |
1391 |
1 |
|
| S0_REG_TX_D2_AMP_XSG |
1386 |
5 |
|
| S0_REG_TX_D1_AMP_XSG |
1381 |
5 |
|
| S0_REG_TX_D0_AMP_XSG |
1376 |
5 |
|
| S0_REG_TX_SEL_VCM_TG |
1374 |
2 |
|
| S0_REG_TXDLY_TG |
1372 |
2 |
|
| S0_REG_TX_ADDMOS_TG |
1371 |
1 |
|
| S0_REG_TX_D2S_SEL_TG |
1370 |
1 |
|
| S0_REG_TXLA_SENDB_TG |
1369 |
1 |
|
| S0_REG_IBRX_BOOSTER_TG |
1368 |
1 |
|
| S0_REG_IBTX_BOOSTER_TG |
1367 |
1 |
|
| S0_REG_EN_M_VALUE_1_TG |
1363 |
4 |
|
| S0_REG_TX_TAMP_TG |
1360 |
3 |
|
| S0_REG_TX_SEL_VCM_XSG |
1358 |
2 |
|
| S0_REG_TXDLY_XSG |
1356 |
2 |
|
| S0_REG_TX_ADDMOS_XSG |
1355 |
1 |
|
| S0_REG_TX_D2S_SEL_XSG |
1354 |
1 |
|
| S0_REG_TXLA_SENDB_XSG |
1353 |
1 |
|
| S0_REG_IBRX_BOOSTER_XSG |
1352 |
1 |
|
| S0_REG_IBTX_BOOSTER_XSG |
1351 |
1 |
|
| S0_REG_EN_M_VALUE_1_XSG |
1347 |
4 |
|
| S0_REG_TX_TAMP_XSG |
1344 |
3 |
|
| S0_REG_TX_PRDRV_CM_TG |
1342 |
2 |
|
| S0_REG_TX_D2_PN_SEL_TG |
1341 |
1 |
|
| S0_REG_TX_D1_PN_SEL_TG |
1340 |
1 |
|
| S0_REG_TX_D0_PN_SEL_TG |
1339 |
1 |
|
| S0_REG_TX_D2_EN_TG |
1338 |
1 |
|
| S0_REG_TX_D1_EN_TG |
1337 |
1 |
|
| S0_REG_TX_D0_EN_TG |
1336 |
1 |
|
| S0_REG_TX_SPDSEL_DIG_TG |
1335 |
1 |
|
| S0_DUMMY_RG2D2C_22 |
1334 |
1 |
|
| S0_REG_RX_CKLC_SEL_TG |
1333 |
1 |
|
| S0_REG_RX_CKDIV2_SEL_TG |
1332 |
1 |
|
| S0_REG_TX_SPDSEL_TG |
1330 |
2 |
|
| S0_REG_TX_CKLC_SEL_TG |
1329 |
1 |
|
| S0_REG_TX_CKDIV2_SEL_TG |
1328 |
1 |
|
| S0_REG_TX_PRDRV_CM_XSG |
1326 |
2 |
|
| S0_REG_TX_D2_PN_SEL_XSG |
1325 |
1 |
|
| S0_REG_TX_D1_PN_SEL_XSG |
1324 |
1 |
|
| S0_REG_TX_D0_PN_SEL_XSG |
1323 |
1 |
|
| S0_REG_TX_D2_EN_XSG |
1322 |
1 |
|
| S0_REG_TX_D1_EN_XSG |
1321 |
1 |
|
| S0_REG_TX_D0_EN_XSG |
1320 |
1 |
|
| S0_REG_TX_SPDSEL_DIG_XSG |
1319 |
1 |
|
| S0_DUMMY_RG2D2C_06 |
1318 |
1 |
|
| S0_REG_RX_CKLC_SEL_XSG |
1317 |
1 |
|
| S0_REG_RX_CKDIV2_SEL_XSG |
1316 |
1 |
|
| S0_REG_TX_SPDSEL_XSG |
1314 |
2 |
|
| S0_REG_TX_CKLC_SEL_XSG |
1313 |
1 |
|
| S0_REG_TX_CKDIV2_SEL_XSG |
1312 |
1 |
|
| S0_REG_ISTANK_SEL_TG |
1309 |
3 |
|
| S0_REG_TIME2_RST_WIDTH_TG |
1307 |
2 |
|
| S0_REG_VI_SEL_TG |
1304 |
3 |
|
| S0_REG_CMU_INJ_MODE_SEL_TG |
1303 |
1 |
|
| S0_REG_CMU_SEL_CSM_TG |
1301 |
2 |
|
| S0_REG_CMU_VCO_COARSE_TG |
1296 |
5 |
|
| S0_REG_ISTANK_SEL_XSG |
1293 |
3 |
|
| S0_REG_TIME2_RST_WIDTH_XSG |
1291 |
2 |
|
| S0_REG_VI_SEL_XSG |
1288 |
3 |
|
| S0_REG_CMU_INJ_MODE_SEL_XSG |
1287 |
1 |
|
| S0_REG_CMU_SEL_CSM_XSG |
1285 |
2 |
|
| S0_REG_CMU_VCO_COARSE_XSG |
1280 |
5 |
|
| S0_DUMMY_RG3130_3100 |
1248 |
32 |
|
| S0_DUMMY_RG3332_3100 |
1216 |
32 |
|
| S0_DUMMY_RG3534_3100 |
1184 |
32 |
|
| S0_DUMMY_RG3736_3100 |
1152 |
32 |
|
| S0_DUMMY_RG3938_3100 |
1120 |
32 |
|
| S0_DUMMY_RG3B3A_3100 |
1088 |
32 |
|
| S0_RU1_CNT |
1082 |
6 |
|
| S0_FRC_OOBS_RSTB |
1081 |
1 |
|
| S0_FRC_XSG |
1080 |
1 |
|
| S0_FRC_TGR |
1079 |
1 |
|
| S0_FRC_TGX |
1078 |
1 |
|
| S0_FRC_BER_NOTIFY |
1077 |
1 |
|
| S0_FRC_CLKRDY |
1076 |
1 |
|
| S0_FRC_RXAUI |
1075 |
1 |
|
| S0_FRC_CLK156_EN |
1074 |
1 |
|
| S0_FRC_SPDSEL1 |
1072 |
2 |
|
| S0_FRC_SPDSEL0 |
1070 |
2 |
|
| S0_FRC_RST_BITERR |
1068 |
2 |
|
| S0_FRC_V2ANALOG |
1066 |
2 |
|
| S0_FRC_RX_DATA_EN |
1064 |
2 |
|
| S0_FRC_RX_CLKWR_EN |
1062 |
2 |
|
| S0_FRC_RX_EN |
1060 |
2 |
|
| S0_FRC_PDOWN |
1058 |
2 |
|
| S0_FRC_CMU_EN |
1057 |
1 |
|
| S0_FRC_EN |
1056 |
1 |
|
| S0_FRC_CLK156_2_EN |
1055 |
1 |
|
| S0_RU0_CNT |
1046 |
9 |
|
| S0_RU2 |
1045 |
1 |
|
| S0_RU1 |
1044 |
1 |
|
| S0_LNK_SG_TMR |
1040 |
4 |
|
| S0_DONE_LVL |
1039 |
1 |
|
| S0_FULLL_LVL |
1038 |
1 |
|
| S0_RU0 |
1037 |
1 |
|
| S0_CHK_TMR |
1033 |
4 |
|
| S0_SYMB_TMR |
1028 |
5 |
|
| S0_EYE_WIDTH |
1025 |
3 |
|
| S0_DIS_AD |
1024 |
1 |
|
| S1_REG_BIAS_PICORE_KP |
1022 |
2 |
|
| S1_REG_INT_INIT |
1008 |
14 |
|
| S1_REG_BIAS_PICORE_KI |
1006 |
2 |
|
| S1_REG_BIAS_STR |
1003 |
3 |
|
| S1_REG_ACC2_MANUAL |
1002 |
1 |
|
| S1_REG_ACC2_PERIOD |
992 |
10 |
|
| S1_REG_BITSEL |
991 |
1 |
|
| S1_REG_EQ_LO_BND2 |
986 |
5 |
|
| S1_REG_EQ_LO_BND1 |
981 |
5 |
|
| S1_REG_EQ_LO_BND0 |
976 |
5 |
|
| S1_REG_CDR_RESET_SEL |
975 |
1 |
|
| S1_REG_CLKLA_AMP |
972 |
3 |
|
| S1_REG_CK25MO_E4 |
971 |
1 |
|
| S1_REG_CK25MO_EN |
970 |
1 |
|
| S1_REG_EQ_UP_BND3 |
965 |
5 |
|
| S1_REG_EQ_UP_BND2 |
960 |
5 |
|
| S1_REG_BIAS_PIFINE_KI |
958 |
2 |
|
| S1_REG_EQ_PERIOD1 |
951 |
7 |
|
| S1_REG_EQ_PERIOD0 |
944 |
7 |
|
| S1_REG_RELOAD_EN |
943 |
1 |
|
| S1_REG_EQ_UP_BND1 |
938 |
5 |
|
| S1_REG_EQ_UP_BND0 |
933 |
5 |
|
| S1_REG_EQ_LO_BND3 |
928 |
5 |
|
| S1_REG_ST2_INIT_1 |
912 |
16 |
|
| S1_REG_BIAS_PIFINE_KP |
910 |
2 |
|
| S1_REG_EQ_PERIOD3 |
903 |
7 |
|
| S1_REG_EQ_PERIOD2 |
896 |
7 |
|
| S1_REG_LPFEN_MANUAL |
895 |
1 |
|
| S1_REG_OCHOLD |
894 |
1 |
|
| S1_REG_OC_SLICER |
893 |
1 |
|
| S1_REG_OC_SELREG |
892 |
1 |
|
| S1_REG_OC_GAIN |
889 |
3 |
|
| S1_REG_EN2_INIT_1 |
885 |
4 |
|
| S1_REG_ST_M_VALUE |
880 |
5 |
|
| S1_REG_ST_M_VALUE_1 |
864 |
16 |
|
| S1_REG_BYPASS_SDM_INT |
863 |
1 |
|
| S1_REG_TIMER_EQ3 |
858 |
5 |
|
| S1_REG_TIMER_EQ2 |
853 |
5 |
|
| S1_REG_TIMER_EQ1 |
848 |
5 |
|
| S1_REG_RX_OEB_CKPIO13 |
847 |
1 |
|
| S1_REG_TIMER_EQ0 |
842 |
5 |
|
| S1_REG_TIMER_DCCAL |
837 |
5 |
|
| S1_REG_TIMER_BER |
832 |
5 |
|
| S1_REG_EQ_SLICER3 |
831 |
1 |
|
| S1_REG_EQ_SLICER2 |
830 |
1 |
|
| S1_REG_EQ_SLICER1 |
829 |
1 |
|
| S1_REG_EQ_SLICER0 |
828 |
1 |
|
| S1_REG_TIMER_EQHOLD3 |
822 |
6 |
|
| S1_REG_TIMER_EQHOLD2 |
816 |
6 |
|
| S1_REG_EQHOLD |
812 |
4 |
|
| S1_REG_TIMER_EQHOLD1 |
806 |
6 |
|
| S1_REG_TIMER_EQHOLD0 |
800 |
6 |
|
| S1_REG_CK25MO_E32 |
798 |
2 |
|
| S1_REG_RX_DBG_SEL |
796 |
2 |
|
| S1_REG_EQ_GAIN3 |
793 |
3 |
|
| S1_REG_EQ_GAIN2 |
790 |
3 |
|
| S1_REG_EQ_GAIN1 |
787 |
3 |
|
| S1_REG_EQ_GAIN0 |
784 |
3 |
|
| S1_REG_OFFSET_ADJR |
780 |
4 |
|
| S1_REG_OOBS_SEN_VAL |
775 |
5 |
|
| S1_REG_OC_PERIOD |
768 |
7 |
|
| S1_REG_VSEL_LREG |
765 |
3 |
|
| S1_REG_LCVCO_TR_3_ |
764 |
1 |
|
| S1_REG_LCVCO_TR_2_ |
763 |
1 |
|
| S1_REG_LCVCO_TR_1_ |
762 |
1 |
|
| S1_REG_LCVCO_TR_0_ |
761 |
1 |
|
| S1_REG_INIT_TIME |
758 |
3 |
|
| S1_REG_CP_TIME |
755 |
3 |
|
| S1_REG_CALIB_TIME |
752 |
3 |
|
| S1_REG_OFFSET_RANGE |
750 |
2 |
|
| S1_REG_OFFSET_AUTOK |
749 |
1 |
|
| S1_REG_EN_KOFFSET |
748 |
1 |
|
| S1_REG_TESTOUT_SEL_1 |
746 |
2 |
|
| S1_REG_TESTOUT_SEL |
744 |
2 |
|
| S1_REG_SQU_TRI |
743 |
1 |
|
| S1_REG_RX_IDLE_SPD |
742 |
1 |
|
| S1_REG_RX_SEL_RXIDLE |
741 |
1 |
|
| S1_REG_RX_EN_TEST |
740 |
1 |
|
| S1_REG_RX_FORCERUN |
739 |
1 |
|
| S1_REG_RX_DATA_EN_SEL |
738 |
1 |
|
| S1_REG_RX_CLKWR_EN_SEL |
737 |
1 |
|
| S1_REG_RESET_MANUAL |
736 |
1 |
|
| S1_REG_TX_SWING25 |
735 |
1 |
|
| S1_REG_TX_VCM_RES |
734 |
1 |
|
| S1_REG_TX_EN_TEST |
733 |
1 |
|
| S1_REG_ZTUNE |
732 |
1 |
|
| S1_REG_ZTEST |
731 |
1 |
|
| S1_REG_TX_SEL_CKRD_DUTY |
730 |
1 |
|
| S1_REG_Z0_PAUTO_K |
729 |
1 |
|
| S1_REG_Z0_PADJR |
725 |
4 |
|
| S1_REG_Z0_NAUTO_K |
724 |
1 |
|
| S1_REG_Z0_NADJR |
720 |
4 |
|
| S1_REG_CMU_SEL_WDCK |
719 |
1 |
|
| S1_REG_CMU_EN_WD |
718 |
1 |
|
| S1_REG_IB_CENTER_FILTER |
717 |
1 |
|
| S1_REG_IB_FILTER |
716 |
1 |
|
| S1_REG_SINGVCO |
715 |
1 |
|
| S1_REG_LCBIAS_LPF_EN |
714 |
1 |
|
| S1_REG_ISTANK_SEL_LS_1_ |
713 |
1 |
|
| S1_REG_ISTANK_SEL_LS_0_ |
712 |
1 |
|
| S1_REG_FLD_DSEL |
711 |
1 |
|
| S1_REG_CMU_VCP_SEL |
710 |
1 |
|
| S1_REG_CMU_AUTO_K |
709 |
1 |
|
| S1_REG_CLKRDY |
707 |
2 |
|
| S1_REG_ADP_TIME |
704 |
3 |
|
| S1_DUMMY_RG1514_3116 |
688 |
16 |
|
| S1_REG_BG |
686 |
2 |
|
| S1_REG_TX_SWING |
684 |
2 |
|
| S1_REG_IBRXSEL |
682 |
2 |
|
| S1_REG_IBTXSEL |
680 |
2 |
|
| S1_REG_DATA_TRANS |
676 |
4 |
|
| S1_REG_EN_M_VALUE |
672 |
4 |
|
| S1_REG_FILTER_OUT0_TG |
667 |
5 |
|
| S1_REG_EQ_SELREG_TG |
663 |
4 |
|
| S1_REG_EQ_IN_TG |
656 |
7 |
|
| S1_REG_FILTER_OUT0_XSG |
651 |
5 |
|
| S1_REG_EQ_SELREG_XSG |
647 |
4 |
|
| S1_REG_EQ_IN_XSG |
640 |
7 |
|
| S1_REG_RX_EQ_BOOST_DC_TG |
639 |
1 |
|
| S1_REG_FILTER_OUT3_TG |
634 |
5 |
|
| S1_REG_FILTER_OUT2_TG |
629 |
5 |
|
| S1_REG_FILTER_OUT1_TG |
624 |
5 |
|
| S1_REG_RX_EQ_BOOST_DC_XSG |
623 |
1 |
|
| S1_REG_FILTER_OUT3_XSG |
618 |
5 |
|
| S1_REG_FILTER_OUT2_XSG |
613 |
5 |
|
| S1_REG_FILTER_OUT1_XSG |
608 |
5 |
|
| S1_REG_ST2_M_VALUE_1_TG |
592 |
16 |
|
| S1_REG_ST2_M_VALUE_1_XSG |
576 |
16 |
|
| S1_REG_CLKLA_EN_TG |
575 |
1 |
|
| S1_REG_RSEL_TG |
573 |
2 |
|
| S1_REG_KI_TG |
570 |
3 |
|
| S1_REG_KD_TG |
569 |
1 |
|
| S1_REG_KP2_TG |
566 |
3 |
|
| S1_REG_KP1_TG |
564 |
2 |
|
| S1_REG_KP1_1_TG |
560 |
4 |
|
| S1_REG_CLKLA_EN_XSG |
559 |
1 |
|
| S1_REG_RSEL_XSG |
557 |
2 |
|
| S1_REG_KI_XSG |
554 |
3 |
|
| S1_REG_KD_XSG |
553 |
1 |
|
| S1_REG_KP2_XSG |
550 |
3 |
|
| S1_REG_KP1_XSG |
548 |
2 |
|
| S1_REG_KP1_1_XSG |
544 |
4 |
|
| S1_REG_PR1_KP_RSEL_TG |
542 |
2 |
|
| S1_REG_PR2_KI_RSEL_TG |
540 |
2 |
|
| S1_REG_OOBS_VCM_TG |
538 |
2 |
|
| S1_REG_PI_HOLD_TG |
537 |
1 |
|
| S1_REG_PI2_HOLD_1_TG |
536 |
1 |
|
| S1_REG_PI_HOLD_1_TG |
535 |
1 |
|
| S1_REG_OFFSET_SR_TG |
533 |
2 |
|
| S1_REG_OFFSET_IH_TG |
531 |
2 |
|
| S1_REG_OOBS_SEL_TG |
530 |
1 |
|
| S1_REG_OOBS_FREQ_SEL_TG |
529 |
1 |
|
| S1_REG_PI_IBX_SEL_TG |
528 |
1 |
|
| S1_REG_PR1_KP_RSEL_XSG |
526 |
2 |
|
| S1_REG_PR2_KI_RSEL_XSG |
524 |
2 |
|
| S1_REG_OOBS_VCM_XSG |
522 |
2 |
|
| S1_REG_PI_HOLD_XSG |
521 |
1 |
|
| S1_REG_PI2_HOLD_1_XSG |
520 |
1 |
|
| S1_REG_PI_HOLD_1_XSG |
519 |
1 |
|
| S1_REG_OFFSET_SR_XSG |
517 |
2 |
|
| S1_REG_OFFSET_IH_XSG |
515 |
2 |
|
| S1_REG_OOBS_SEL_XSG |
514 |
1 |
|
| S1_REG_OOBS_FREQ_SEL_XSG |
513 |
1 |
|
| S1_REG_PI_IBX_SEL_XSG |
512 |
1 |
|
| S1_REG_RX_EN_SELF_TG |
511 |
1 |
|
| S1_REG_OOBS_RXIDLE_MANUAL_TG |
510 |
1 |
|
| S1_REG_OOBS_CKSEL_TG |
509 |
1 |
|
| S1_REG_PI2_M_MODE_1_TG |
508 |
1 |
|
| S1_REG_PI_M_MODE_1_TG |
507 |
1 |
|
| S1_REG_PI_M_MODE_TG |
506 |
1 |
|
| S1_REG_EN2_M_VALUE_1_TG |
502 |
4 |
|
| S1_REG_OOBS_NSQDLY_SEL_TG |
501 |
1 |
|
| S1_REG_OOBS_SWEN_TG |
500 |
1 |
|
| S1_REG_RSSI_SEN_TG |
498 |
2 |
|
| S1_REG_OOBS_CALI_TG |
496 |
2 |
|
| S1_REG_RX_EN_SELF_XSG |
495 |
1 |
|
| S1_REG_OOBS_RXIDLE_MANUAL_XSG |
494 |
1 |
|
| S1_REG_OOBS_CKSEL_XSG |
493 |
1 |
|
| S1_REG_PI2_M_MODE_1_XSG |
492 |
1 |
|
| S1_REG_PI_M_MODE_1_XSG |
491 |
1 |
|
| S1_REG_PI_M_MODE_XSG |
490 |
1 |
|
| S1_REG_EN2_M_VALUE_1_XSG |
486 |
4 |
|
| S1_REG_OOBS_NSQDLY_SEL_XSG |
485 |
1 |
|
| S1_REG_OOBS_SWEN_XSG |
484 |
1 |
|
| S1_REG_RSSI_SEN_XSG |
482 |
2 |
|
| S1_REG_OOBS_CALI_XSG |
480 |
2 |
|
| S1_REG_DIVIDE_NUM_TG |
474 |
6 |
|
| S1_REG_LOCK_DN_LIMIT_TG |
464 |
10 |
|
| S1_REG_DIVIDE_NUM_XSG |
458 |
6 |
|
| S1_REG_LOCK_DN_LIMIT_XSG |
448 |
10 |
|
| S1_REG_LCVCO_HSMODE_TG |
447 |
1 |
|
| S1_REG_CMU_LOOP_DIVN_TG |
442 |
5 |
|
| S1_REG_LOCK_UP_LIMIT_TG |
432 |
10 |
|
| S1_REG_LCVCO_HSMODE_XSG |
431 |
1 |
|
| S1_REG_CMU_LOOP_DIVN_XSG |
426 |
5 |
|
| S1_REG_LOCK_UP_LIMIT_XSG |
416 |
10 |
|
| S1_REG_ISTANK_SEL_HS_TG_1 |
415 |
1 |
|
| S1_REG_ISTANK_SEL_HS_TG_0 |
414 |
1 |
|
| S1_REG_CMU_SEL_CP_TG |
412 |
2 |
|
| S1_REG_CMU_SELPREDIV_TG |
410 |
2 |
|
| S1_REG_CMU_LOOP_DIV4_TG |
408 |
2 |
|
| S1_REG_CMU_ICP_SEL_TG |
404 |
4 |
|
| S1_REG_CMU_SEL_R_TG_3 |
403 |
1 |
|
| S1_REG_CMU_SEL_R_TG_2_0 |
400 |
3 |
|
| S1_REG_ISTANK_SEL_HS_XSG_1 |
399 |
1 |
|
| S1_REG_ISTANK_SEL_HS_XSG_0 |
398 |
1 |
|
| S1_REG_CMU_SEL_CP_XSG |
396 |
2 |
|
| S1_REG_CMU_SELPREDIV_XSG |
394 |
2 |
|
| S1_REG_CMU_LOOP_DIV4_XSG |
392 |
2 |
|
| S1_REG_CMU_ICP_SEL_XSG |
388 |
4 |
|
| S1_REG_CMU_SEL_R_XSG_3 |
387 |
1 |
|
| S1_REG_CMU_SEL_R_XSG_2_0 |
384 |
3 |
|
| S1_REG_TXLA_IBXSEL_TG |
383 |
1 |
|
| S1_REG_TX_D2_AMP_TG |
378 |
5 |
|
| S1_REG_TX_D1_AMP_TG |
373 |
5 |
|
| S1_REG_TX_D0_AMP_TG |
368 |
5 |
|
| S1_REG_TXLA_IBXSEL_XSG |
367 |
1 |
|
| S1_REG_TX_D2_AMP_XSG |
362 |
5 |
|
| S1_REG_TX_D1_AMP_XSG |
357 |
5 |
|
| S1_REG_TX_D0_AMP_XSG |
352 |
5 |
|
| S1_REG_TX_SEL_VCM_TG |
350 |
2 |
|
| S1_REG_TXDLY_TG |
348 |
2 |
|
| S1_REG_TX_ADDMOS_TG |
347 |
1 |
|
| S1_REG_TX_D2S_SEL_TG |
346 |
1 |
|
| S1_REG_TXLA_SENDB_TG |
345 |
1 |
|
| S1_REG_IBRX_BOOSTER_TG |
344 |
1 |
|
| S1_REG_IBTX_BOOSTER_TG |
343 |
1 |
|
| S1_REG_EN_M_VALUE_1_TG |
339 |
4 |
|
| S1_REG_TX_TAMP_TG |
336 |
3 |
|
| S1_REG_TX_SEL_VCM_XSG |
334 |
2 |
|
| S1_REG_TXDLY_XSG |
332 |
2 |
|
| S1_REG_TX_ADDMOS_XSG |
331 |
1 |
|
| S1_REG_TX_D2S_SEL_XSG |
330 |
1 |
|
| S1_REG_TXLA_SENDB_XSG |
329 |
1 |
|
| S1_REG_IBRX_BOOSTER_XSG |
328 |
1 |
|
| S1_REG_IBTX_BOOSTER_XSG |
327 |
1 |
|
| S1_REG_EN_M_VALUE_1_XSG |
323 |
4 |
|
| S1_REG_TX_TAMP_XSG |
320 |
3 |
|
| S1_REG_TX_PRDRV_CM_TG |
318 |
2 |
|
| S1_REG_TX_D2_PN_SEL_TG |
317 |
1 |
|
| S1_REG_TX_D1_PN_SEL_TG |
316 |
1 |
|
| S1_REG_TX_D0_PN_SEL_TG |
315 |
1 |
|
| S1_REG_TX_D2_EN_TG |
314 |
1 |
|
| S1_REG_TX_D1_EN_TG |
313 |
1 |
|
| S1_REG_TX_D0_EN_TG |
312 |
1 |
|
| S1_REG_TX_SPDSEL_DIG_TG |
311 |
1 |
|
| S1_DUMMY_RG2D2C_22 |
310 |
1 |
|
| S1_REG_RX_CKLC_SEL_TG |
309 |
1 |
|
| S1_REG_RX_CKDIV2_SEL_TG |
308 |
1 |
|
| S1_REG_TX_SPDSEL_TG |
306 |
2 |
|
| S1_REG_TX_CKLC_SEL_TG |
305 |
1 |
|
| S1_REG_TX_CKDIV2_SEL_TG |
304 |
1 |
|
| S1_REG_TX_PRDRV_CM_XSG |
302 |
2 |
|
| S1_REG_TX_D2_PN_SEL_XSG |
301 |
1 |
|
| S1_REG_TX_D1_PN_SEL_XSG |
300 |
1 |
|
| S1_REG_TX_D0_PN_SEL_XSG |
299 |
1 |
|
| S1_REG_TX_D2_EN_XSG |
298 |
1 |
|
| S1_REG_TX_D1_EN_XSG |
297 |
1 |
|
| S1_REG_TX_D0_EN_XSG |
296 |
1 |
|
| S1_REG_TX_SPDSEL_DIG_XSG |
295 |
1 |
|
| S1_DUMMY_RG2D2C_06 |
294 |
1 |
|
| S1_REG_RX_CKLC_SEL_XSG |
293 |
1 |
|
| S1_REG_RX_CKDIV2_SEL_XSG |
292 |
1 |
|
| S1_REG_TX_SPDSEL_XSG |
290 |
2 |
|
| S1_REG_TX_CKLC_SEL_XSG |
289 |
1 |
|
| S1_REG_TX_CKDIV2_SEL_XSG |
288 |
1 |
|
| S1_REG_ISTANK_SEL_TG |
285 |
3 |
|
| S1_REG_TIME2_RST_WIDTH_TG |
283 |
2 |
|
| S1_REG_VI_SEL_TG |
280 |
3 |
|
| S1_REG_CMU_INJ_MODE_SEL_TG |
279 |
1 |
|
| S1_REG_CMU_SEL_CSM_TG |
277 |
2 |
|
| S1_REG_CMU_VCO_COARSE_TG |
272 |
5 |
|
| S1_REG_ISTANK_SEL_XSG |
269 |
3 |
|
| S1_REG_TIME2_RST_WIDTH_XSG |
267 |
2 |
|
| S1_REG_VI_SEL_XSG |
264 |
3 |
|
| S1_REG_CMU_INJ_MODE_SEL_XSG |
263 |
1 |
|
| S1_REG_CMU_SEL_CSM_XSG |
261 |
2 |
|
| S1_REG_CMU_VCO_COARSE_XSG |
256 |
5 |
|
| S1_DUMMY_RG3130_3100 |
224 |
32 |
|
| S1_DUMMY_RG3332_3100 |
192 |
32 |
|
| S1_DUMMY_RG3534_3100 |
160 |
32 |
|
| S1_DUMMY_RG3736_3100 |
128 |
32 |
|
| S1_DUMMY_RG3938_3100 |
96 |
32 |
|
| S1_DUMMY_RG3B3A_3100 |
64 |
32 |
|
| S1_DUMMY_RG3D3C_31_26 |
58 |
6 |
|
| S1_DUMMY_RG3D3C_25 |
57 |
1 |
|
| S1_DUMMY_RG3D3C_24 |
56 |
1 |
|
| S1_DUMMY_RG3D3C_23 |
55 |
1 |
|
| S1_DUMMY_RG3D3C_22 |
54 |
1 |
|
| S1_DUMMY_RG3D3C_21 |
53 |
1 |
|
| S1_DUMMY_RG3D3C_20 |
52 |
1 |
|
| S1_DUMMY_RG3D3C_19 |
51 |
1 |
|
| S1_DUMMY_RG3D3C_18 |
50 |
1 |
|
| S1_DUMMY_RG3D3C_17_16 |
48 |
2 |
|
| S1_DUMMY_RG3D3C_15_14 |
46 |
2 |
|
| S1_DUMMY_RG3D3C_13_12 |
44 |
2 |
|
| S1_DUMMY_RG3D3C_11_10 |
42 |
2 |
|
| S1_DUMMY_RG3D3C_9_8 |
40 |
2 |
|
| S1_DUMMY_RG3D3C_7_6 |
38 |
2 |
|
| S1_DUMMY_RG3D3C_5_4 |
36 |
2 |
|
| S1_DUMMY_RG3D3C_3_2 |
34 |
2 |
|
| S1_DUMMY_RG3D3C_1 |
33 |
1 |
|
| S1_DUMMY_RG3D3C_0 |
32 |
1 |
|
| S1_DUMMY_RG3F3E_31 |
31 |
1 |
|
| S1_DUMMY_RG3F3E_30_22 |
22 |
9 |
|
| S1_DUMMY_RG3F3E_21 |
21 |
1 |
|
| S1_DUMMY_RG3F3E_20 |
20 |
1 |
|
| S1_DUMMY_RG3F3E_19_16 |
16 |
4 |
|
| S1_DUMMY_RG3F3E_15 |
15 |
1 |
|
| S1_DUMMY_RG3F3E_14 |
14 |
1 |
|
| S1_DUMMY_RG3F3E_13 |
13 |
1 |
|
| S1_DUMMY_RG3F3E_12_9 |
9 |
4 |
|
| S1_DUMMY_RG3F3E_8_4 |
4 |
5 |
|
| S1_DUMMY_RG3F3E_3_1 |
1 |
3 |
|
| S1_DUMMY_RG3F3E_0 |
0 |
1 |
|