Realtek switch SoC docs

cypress feature PHY_SERDES

Registers

Offset Name Summary
PHY_SERDES
a000 SDS0_1_XSG0
a100 SDS0_1_XSG1
a300 SDS0_1_ANA_RG_EXT
a400 SDS2_3_XSG0
a500 SDS2_3_XSG1
a700 SDS2_3_ANA_RG_EXT
a800 SDS4_5_XSG0
a900 SDS4_5_XSG1
ab00 SDS4_5_ANA_RG_EXT
ac00 SDS6_7_XSG0
ad00 SDS6_7_XSG1
af00 SDS6_7_ANA_RG_EXT
b000 SDS8_9_XSG0
b100 SDS8_9_XSG1
b200 SDS8_9_TGRX
b300 SDS8_9_ANA_TG
b400 SDS10_11_XSG0
b500 SDS10_11_XSG1
b700 SDS10_11_ANA_RG_EXT
b800 SDS12_13_XSG0
b900 SDS12_13_XSG1
ba00 SDS12_13_TGRX
bb00 SDS12_13_ANA_TG