longan register: LINK_DELAY_CTRL
Details
- Name
- LINK_DELAY_CTRL
- Offset
- cb0c
- Feature
- MAC_CONTROL
Description
Link update delay controller
default: 0x0000_002a
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 25 | 7 |
|
| LINK_DN_TMR_EN | 24 | 1 |
Link down delay timer enable
|
| LINK_DN_TMR | 16 | 8 |
Link down delay timer |
| BYPASS_ABLTY_LOCK | 15 | 1 |
Link status port ability bypass |
| TX_IDLE_TMR | 7 | 8 |
TX Idle timer delay to link-up 1us per bit |
| LINKUP_DELAY_10G_5G | 5 | 2 |
MAC to PHY link up info (10G or 5G)
|
| LINKUP_DELAY_2P5G_1000M_100M | 3 | 2 |
MAC to PHY link up info (2G5, 2pair 2G5, 2pair 1000M, 1000M or 100Mbit)
|
| LINKUP_DELAY_10M | 0 | 3 |
MAC to PHY link up info (10Mbit)
|