Realtek switch SoC docs

longan feature MAC_CONTROL

Registers

Offset Name Summary
MAC_CONTROL
007c BONDING_REDEFINE_REG
0280 MAC_SSC_CTRL_0
0284 MAC_SSC_CTRL_1
0288 MAC_SSC_CTRL_2
028c MAC_SSC_CTRL_3
0290 MAC_SSC_CTRL_4
3260 MAC_PORT_CTRL
3264 HALF_CHG_CTRL
3268 MAC_L2_PORT_CTRL
326c MAC_L2_PORT_MAX_LEN_CTRL
3270 DMY_REG0_PER_PORT_MAC
a3a0 MAC_L2_CPU_MAX_LEN_CTRL
a3a4 DMY_REG0_ALE_GLB
c6e0 MAC_GLB_CTRL
c6e4 MAC_EEPROM_DOWN_LOAD_CNTRL
c6e8 MAC_EEPROM_DOWN_LOAD_STS
c6ec MAC_EEPROM_DOWN_LOAD_MAC_POS
c6f0 MAC_EEPROM_DOWN_LOAD_SERDES_POS
c6f4 MAC_EEPROM_DOWN_LOAD_PHY_POS
c6f8 MAC_EEPROM_DOWN_LOAD_GROUP_MAC_POS
c6fc MAC_EFUSE_CTRL
c700 MAC_L2_GLOBAL_CTRL0
c704 MAC_L2_GLOBAL_CTRL1
c708 MAC_L2_PADDING_SEL
c70c MAC_L2_CPU_PORT_CTRL
c710 MAC_L2_CPU_TAG_ID_CTRL
c714 MAC_L2_ADDR_CTRL
c71c DMY_REG1_GLB_CTRL
ca00 SMI_GLB_CTRL

Global control register of the SMI busses 0-3.

ca04 SMI_MAC_TYPE_CTRL

SMI MAC port PHY type

ca08 SMI_PORT0_15_POLLING_SEL

SMI Port 0 - 15 polling selector

ca0c SMI_PORT16_27_POLLING_SEL

SMI Port 16 - 27 polling selector

ca10 SMI_PRVTE_POLLING_CTRL

SMI Private polling controller

ca14 MDIO_FREE_CNT_CTRL

MDIO Free counter controller

ca18 SMI_10GPHY_POLLING_SEL_0

10G/2.5G GPHY internal resolution register

ca1c MAC_FORCE_MODE_CTRL

Per port MAC force mode controller

ca90 SMI_POLL_CTRL

SMI Polling mask

ca94 SMI_REG_CHK1_CTRL0
ca98 SMI_REG_CHK1_CTRL1
ca9c SMI_REG_CHK1_PMSK
caa0 SMI_REG_CHK1_DATA
caa4 SMI_REG_CHK1_DATA_10G
caa8 SMI_REG_CHK1_RESULT
caac SMI_REG_CHK2_CTRL0
cab0 SMI_REG_CHK2_CTRL1
cab4 SMI_REG_CHK2_PMSK
cab8 SMI_REG_CHK2_DATA
cabc SMI_REG_CHK2_DATA_10G
cac0 SMI_REG_CHK2_RESULT
cac4 SMI_REG_CHK3_CTRL0
cac8 SMI_REG_CHK3_CTRL1
cacc SMI_REG_CHK3_PMSK
cad0 SMI_REG_CHK3_DATA
cad4 SMI_REG_CHK3_DATA_10G
cad8 SMI_REG_CHK3_RESULT
cadc SMI_REG_CHK4_CTRL0
cae0 SMI_REG_CHK4_CTRL1
cae4 SMI_REG_CHK4_PMSK
cae8 SMI_REG_CHK4_DATA
caec SMI_REG_CHK4_DATA_10G
caf0 SMI_REG_CHK4_RESULT
caf4 SMI_REG_CHK5_CTRL0
caf8 SMI_REG_CHK5_CTRL1
cafc SMI_REG_CHK5_PMSK
cb00 SMI_REG_CHK5_DATA
cb04 SMI_REG_CHK5_DATA_10G
cb08 SMI_REG_CHK5_RESULT
cb0c LINK_DELAY_CTRL

Link update delay controller

cb10 MAC_LINK_STS

Link status as the MAC sees it.

cb14 MAC_LINK_MEDIA_STS
cb18 MAC_LINK_SPD_STS
cb28 MAC_LINK_DUP_STS
cb2c MAC_TX_PAUSE_STS
cb30 MAC_RX_PAUSE_STS
cb34 MAC_EEE_ABLTY
cb38 MAC_MSTR_SLV_STS
cb3c MAC_MSTR_SLV_FAULT_STS
cb40 PHY_LINK_STS
cb44 PHY_LINK_MEDIA_STS
cb48 PHY_LINK_SPD_STS
cb58 PHY_LINK_DUP_STS
cb5c PHY_TX_PAUSE_STS
cb60 PHY_RX_PAUSE_STS
cb64 PHY_EEE_ABLTY
cb68 PHY_MSTR_SLV_STS
cb6c PHY_MSTR_SLV_FAULT_STS
cb70 SMI_ACCESS_PHY_CTRL_0

PHY port select and PHY broadcast control register 0

cb74 SMI_ACCESS_PHY_CTRL_1

MDIO operations register

cb78 SMI_ACCESS_PHY_CTRL_2

MDIO Data IO register

cb7c SMI_ACCESS_PHY_CTRL_3

MMD offloading register

cb80 SMI_PORT0_5_ADDR_CTRL

SMI port 0 - 5 address mapping controller

cb84 SMI_PORT6_11_ADDR_CTRL

SMI port 6 - 11 address mapping controller

cb88 SMI_PORT12_17_ADDR_CTRL

SMI port 12 - 17 address mapping controller

cb8c SMI_PORT18_23_ADDR_CTRL

SMI port 18 - 23 address mapping controller

cb90 SMI_PORT24_27_ADDR_CTRL

SMI port 24 - 27 address mapping controller

cb94 SDS_MODE_ADJ_CTRL
cb98 SMI_CTRL

SMI Controller

cb9c EXT_SMI_ACCESS_CTRL
cba0 DMY_REG0_SMI_CTRL
cba4 RLFD_CTRL
cba8 RLFD_10G_ADDR
cbac UNI_DIR_CTRL
cbb0 SMI_10GPHY_POLLING_SEL_1

MDIO device and register address for polling the 10G/2G5 PHY internal …

cbb4 SMI_10GPHY_POLLING_REG0_CFG

Reg 0 for polling 10G and 2G5 PHY

cbb8 SMI_10GPHY_POLLING_REG9_CFG

Reg 9 for polling 10G and 2G5 PHY

cbbc SMI_10GPHY_POLLING_REG10_CFG

Reg 10 for polling 10G and 2G5 PHY

e288 DMY_REG0_CHIP_AFE