longan register: SMI_CTRL
Details
- Name
- SMI_CTRL
- Offset
- cb98
- Feature
- MAC_CONTROL
Description
SMI Controller
default: 0x00f0_0000
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 24 | 8 |
|
| SMI3_MDC_EN | 23 | 1 |
SMI Controller 3 MDIO Clock output enable
|
| SMI2_MDC_EN | 22 | 1 |
SMI Controller 2 MDIO Clock output enable
|
| SMI1_MDC_EN | 21 | 1 |
SMI Controller 1 MDIO Clock output enable
|
| SMI0_MDC_EN | 20 | 1 |
SMI Controller 0 MDIO Clock output enable
|
| SDS_MDX_DLY_CFG | 16 | 4 |
SDS inband MDX delay timing |
| SMI3_DLY_CFG | 12 | 4 |
SMI 3 MDX delay timing |
| SMI2_DLY_CFG | 8 | 4 |
SMI 2 MDX delay timing |
| SMI1_DLY_CFG | 4 | 4 |
SMI 1 MDX delay timing |
| SMI0_DLY_CFG | 0 | 4 |
SMI 0 MDX delay timing |