Realtek switch SoC docs

longan register: SMI_GLB_CTRL

Details

Name
SMI_GLB_CTRL
Offset
ca00
Feature
MAC_CONTROL

Description

Global control register of the SMI busses 0-3. Frequency, clause 22/45, automatic polling (for medium detection) can be configured for each bus indidually.

default: 0x0ff8_5500

Fields

Name LSB Bits Description
RESERVED 29 3
SMI_GLB_RST 28 1

SMI global reset

Resets all SMI controllers, self-clears

  • 0b0: nop
  • 0b1: reset
SMI3_POLLING_PARK_SEL 27 1

SMI controller 3 Polling Park Page

Park page during polling

  • 0b0: no park
  • 0b1: park
SMI2_POLLING_PARK_SEL 26 1

SMI controller 2 Polling Park Page

Park page during polling

  • 0b0: no park
  • 0b1: park
SMI1_POLLING_PARK_SEL 25 1

SMI controller 1 Polling Park Page

Park page during polling

  • 0b0: no park
  • 0b1: park
SMI0_POLLING_PARK_SEL 24 1

SMI controller 0 Polling Park Page

Park page during polling

  • 0b0: no park
  • 0b1: park
SMI3_POLL_SEL 23 1

SMI controller 3 polling frequency

Only valid for the Gigabit PHY and 10Gbit PHY

  • 0b0: standard register
  • 0b1: internal resolution register
SMI2_POLL_SEL 22 1

SMI controller 2 polling frequency

Only valid for the Gigabit PHY and 10Gbit PHY

  • 0b0: standard register
  • 0b1: internal resolution register
SMI1_POLL_SEL 21 1

SMI controller 1 polling frequency

Only valid for the Gigabit PHY and 10Gbit PHY

  • 0b0: standard register
  • 0b1: internal resolution register
SMI0_POLL_SEL 20 1

SMI controller 0 polling frequency

Only valid for the Gigabit PHY and 10Gbit PHY

  • 0b0: standard register
  • 0b1: internal resolution register
SMI3_INTF_SEL 19 1

SMI controller 3 interface selection

Gigabit PHY is clause 22 10G Phy is clause 45

  • 0b0: clause 22
  • 0b1: clause 45
SMI2_INTF_SEL 18 1

SMI controller 2 interface selection

Gigabit PHY is clause 22 10G Phy is clause 45

  • 0b0: clause 22
  • 0b1: clause 45
SMI1_INTF_SEL 17 1

SMI controller 1 interface selection

Gigabit PHY is clause 22 10G Phy is clause 45

  • 0b0: clause 22
  • 0b1: clause 45
SMI0_INTF_SEL 16 1

SMI controller 0 interface selection

Gigabit PHY is clause 22 10G Phy is clause 45

  • 0b0: clause 22
  • 0b1: clause 45
SMI3_FREQ_SEL 14 2

SMI controller 3 interface frequency

  • 0x0: 1.25 MHz
  • 0x1: 2.5 MHz
  • 0x2: 5 MHz
  • 0x3: 10 MHz
SMI2_FREQ_SEL 12 2

SMI controller 2 interface frequency

  • 0x0: 1.25 MHz
  • 0x1: 2.5 MHz
  • 0x2: 5 MHz
  • 0x3: 10 MHz
SMI1_FREQ_SEL 10 2

SMI controller 1 interface frequency

  • 0x0: 1.25 MHz
  • 0x1: 2.5 MHz
  • 0x2: 5 MHz
  • 0x3: 10 MHz
SMI0_FREQ_SEL 8 2

SMI controller 0 interface frequency

  • 0x0: 1.25 MHz
  • 0x1: 2.5 MHz
  • 0x2: 5 MHz
  • 0x3: 10 MHz
SMI3_PREAMBLE_SEL 7 1

SMI controller 3 preamble

Preamble for following commands, the first command always has a 32 bit preamble

  • 0b0: 32 bit
  • 0b1: 1 bit
SMI2_PREAMBLE_SEL 6 1

SMI controller 2 preamble

Preamble for following commands, the first command always has a 32 bit preamble

  • 0b0: 32 bit
  • 0b1: 1 bit
SMI1_PREAMBLE_SEL 5 1

SMI controller 1 preamble

Preamble for following commands, the first command always has a 32 bit preamble

  • 0b0: 32 bit
  • 0b1: 1 bit
SMI0_PREAMBLE_SEL 4 1

SMI controller 0 preamble

Preamble for following commands, the first command always has a 32 bit preamble

  • 0b0: 32 bit
  • 0b1: 1 bit
SMI3_BROADCAST_SET_EN 3 1

SMI controller 3 broadcast enable

  • 0b0: disable
  • 0b1: enable
SMI2_BROADCAST_SET_EN 2 1

SMI controller 2 broadcast enable

  • 0b0: disable
  • 0b1: enable
SMI1_BROADCAST_SET_EN 1 1

SMI controller 1 broadcast enable

  • 0b0: disable
  • 0b1: enable
SMI0_BROADCAST_SET_EN 0 1

SMI controller 0 broadcast enable

  • 0b0: disable
  • 0b1: enable