longan register: SOC_BIST_CTRL5
Details
- Name
- SOC_BIST_CTRL5
- Offset
- e140
- Feature
- BIST_BISR
Fields
| Name | LSB | Bits | Description |
|---|---|---|---|
| RESERVED | 16 | 16 |
|
| BIST_MODE | 15 | 1 |
|
| BIST_MODE_OCP | 14 | 1 |
|
| DRF_BIST_MODE | 13 | 1 |
|
| DRF_BIST_MODE_OCP | 12 | 1 |
|
| DRF_TEST_RESUME | 11 | 1 |
|
| DRF_TEST_RESUME_OCP | 10 | 1 |
|
| CPU1_DRF_BIST0_START_PAUSE | 9 | 1 |
|
| CPU1_DRF_BIST1_START_PAUSE | 8 | 1 |
|
| SRAM_DRF_START_PAUSE_0 | 7 | 1 |
|
| CPU1_BIST0_DONE | 6 | 1 |
|
| CPU1_BIST1_DONE | 5 | 1 |
|
| CPU1_DRF_BIST0_DONE | 4 | 1 |
|
| CPU1_DRF_BIST1_DONE | 3 | 1 |
|
| SRAM_BIST_DONE_0 | 2 | 1 |
|
| SRAM_DRF_BIST_DONE_0 | 1 | 1 |
|
| SRAM_ROM_BIST_DONE | 0 | 1 |
|