gpio_control

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gpio_control [2022/04/22 20:24] – Move pinmuxing down svanheulegpio_control [2023/02/28 09:24] (current) – oliver
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 | 0x14 | IMR_LOW    | Low port interrupt mask register. Each port has two bits to indicate on which edges the pin should trigger. Set the lowest bit to trigger on falling edges, the highest bit to trigger on rising edges, or both to trigger on both edges. \\ Register is packed as two big-endian U16 values, the first port at sub-offset 0x0, the second at sub-offset 0x2. | | 0x14 | IMR_LOW    | Low port interrupt mask register. Each port has two bits to indicate on which edges the pin should trigger. Set the lowest bit to trigger on falling edges, the highest bit to trigger on rising edges, or both to trigger on both edges. \\ Register is packed as two big-endian U16 values, the first port at sub-offset 0x0, the second at sub-offset 0x2. |
 | 0x18 | IMR_HIGH   | High port interrupt mask register, see IMR_LOW.\\ Register is packed as two big-endian U16 values, the third port at sub-offset 0x0, the fourth at sub-offset 0x2. | | 0x18 | IMR_HIGH   | High port interrupt mask register, see IMR_LOW.\\ Register is packed as two big-endian U16 values, the third port at sub-offset 0x0, the fourth at sub-offset 0x2. |
 +| 0x38 | C0_IER     | (optional) VPE0 interrupt enable register.\\ Enables routing of GPIO interrupts to VPE0. |
 +| 0x3C | C1_IER     | (optional) VPE1 interrupt enable register.\\ Enables routing of GPIO interrupts to VPE1. |
  
 ===== RTL8380 pin muxing ===== ===== RTL8380 pin muxing =====
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 | UART1 | 116 | ? | RX | Setting BIT(4) in GMII_INTF_SEL (0xBB001000) enables UART1, Clearing BIT(4) selects SPI_SLAVE mode. | | UART1 | 116 | ? | RX | Setting BIT(4) in GMII_INTF_SEL (0xBB001000) enables UART1, Clearing BIT(4) selects SPI_SLAVE mode. |
 | :::   | 117 | ? | TX | ::: | | :::   | 117 | ? | TX | ::: |
-| JTAG | 29 | 12 | TMS   | BIT(2) and BIT(3) in GMII_INTF_SEL (0xBB001000) allow selecting the JTAG interface. |+| GPIO8 | ? | 8 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO9 | ? | 9 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| JTAG | 29 | 12 | TMS   | BIT(2) and BIT(3) in GMII_INTF_SEL (0xBB001000) allow selecting the JTAG interface. \\ Set to 0 for JTAG (default), 2 for GPIO. |
 | :::  | 28 | 13 | TCK   | ::: | | :::  | 28 | 13 | TCK   | ::: |
 | :::  | 32 | 14 | /TRST | ::: | | :::  | 32 | 14 | /TRST | ::: |
 | :::  | 30 | 10 | TDO   | ::: | | :::  | 30 | 10 | TDO   | ::: |
 | :::  | 31 | 11 | TDI   | ::: | | :::  | 31 | 11 | TDI   | ::: |
-| GPIO15 | ? | 15 | N/A | Configured by the [[GS310TP]], no known mux or pin location | +| GPIO15 | ? | 15 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location | 
-| GPIO16 | ? | 16 | N/A | Configured by the [[GS310TP]], no known mux or pin location | +| GPIO16 | ? | 16 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location | 
-| GPIO17 | ? | 17 | N/A | Configured by the [[GS310TP]], no known mux or pin location | +| GPIO17 | ? | 17 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location | 
-| GPIO18 | ? | 18 | N/A | Configured by the [[GS310TP]], no known mux or pin location |+| GPIO18 | ? | 18 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO19 | ? | 19 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO20 | ? | 20 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO21 | ? | 21 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO22 | ? | 22 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
 +| GPIO23 | ? | 23 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location | 
  
 ===== RTL8390 pin muxing ===== ===== RTL8390 pin muxing =====
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 ===== External GPIO ===== ===== External GPIO =====
 The SoCs have been designed with the [[RTL8231]] GPIO expanders in mind as a first-class citizen. The SoCs have been designed with the [[RTL8231]] GPIO expanders in mind as a first-class citizen.
-A hardware peripheral is present that can keep track of the state of one (or two on RTL9310) RTL8231 chip(s).+A hardware peripheral is present that can keep track of the state of one (or two on RTL93xx) RTL8231 chip(s). 
 +The SoC's have dedicated pins and controllers for this task. For rtl930x B6 `EXT_GPIO_MDIO` and A5 `EXT_GPIO_MDC` For rtl931x, AM25: `GPIO_MDC` and AL25: `GPIO_MDIO`. This does require the RTL8231 connected to only function as GPIO expander. This should not be confused with the dedicated `LED_MDxx` pins!
  
 To allow direct access to the devices, a raw command can be sent. For RTL8380 and RTL8390, there is no indication of request failure. RTL9300 and RTL9310 do have a flag to indicate failed read commands. To allow direct access to the devices, a raw command can be sent. For RTL8380 and RTL8390, there is no indication of request failure. RTL9300 and RTL9310 do have a flag to indicate failed read commands.
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 | 0x1188 | ISR_LOW    | Interrupt status register | | 0x1188 | ISR_LOW    | Interrupt status register |
 | 0x118C | ISR_HIGH   | Interrupt status register | | 0x118C | ISR_HIGH   | Interrupt status register |
 +
 +==== RTL930x muxing ====
 +The RTL930x doesn't have a dedicated muxing section in the address space. Instead, the GPIO pin muxing is all over the SoC's addressing space, so this will be a challange. A dedicated page exists to inventory the [[rtl93xx:gpio_space|GPIO mux registers]].
  • gpio_control.1650659045.txt.gz
  • Last modified: 2022/04/22 20:24
  • by svanheule