Differences

This shows you the differences between two versions of the page.

--- gpio_control [2022/04/22 20:28] – Add Cx_IER registers svanheule
+++ gpio_control [2025/01/15 10:56] (current) – Update RTL8390 pin muxing table svanheule
@@ Line 30: / Line 30: @@
 | UART1 | 116 | ? | RX | Setting BIT(4) in GMII_INTF_SEL (0xBB001000) enables UART1, Clearing BIT(4) selects SPI_SLAVE mode. |
 | :::   | 117 | ? | TX | ::: |
-| JTAG | 29 | 12 | TMS   | BIT(2) and BIT(3) in GMII_INTF_SEL (0xBB001000) allow selecting the JTAG interface. |
+| GPIO8 | ? | 8 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| GPIO9 | ? | 9 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| JTAG | 29 | 12 | TMS   | BIT(2) and BIT(3) in GMII_INTF_SEL (0xBB001000) allow selecting the JTAG interface. \\ Set to 0 for JTAG (default), 2 for GPIO. |
 | :::  | 28 | 13 | TCK   | ::: |
 | :::  | 32 | 14 | /TRST | ::: |
 | :::  | 30 | 10 | TDO   | ::: |
 | :::  | 31 | 11 | TDI   | ::: |
-| GPIO15 | ? | 15 | N/A | Configured by the [[GS310TP]], no known mux or pin location |
+| GPIO15 | ? | 15 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location |
-| GPIO16 | ? | 16 | N/A | Configured by the [[GS310TP]], no known mux or pin location |
+| GPIO16 | ? | 16 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location |
-| GPIO17 | ? | 17 | N/A | Configured by the [[GS310TP]], no known mux or pin location |
+| GPIO17 | ? | 17 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location |
-| GPIO18 | ? | 18 | N/A | Configured by the [[GS310TP]], no known mux or pin location |
+| GPIO18 | ? | 18 | N/A | Configured by the [[GS310TP]] and [[GS1900-24EP]], no known mux or pin location |
+| GPIO19 | ? | 19 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| GPIO20 | ? | 20 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| GPIO21 | ? | 21 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| GPIO22 | ? | 22 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
+| GPIO23 | ? | 23 | N/A | Configured by the [[GS1900-24EP]], no known mux or pin location |
 ===== RTL8390 pin muxing =====
@@ Line 44: / Line 51: @@
 ^ Peripheral ^ Package pin ^ GPIO index ^ Alternative function ^ Pin configuration ^
 | System LED |  | 0 | sys-led | Use the SYS_LED_EN bit in LED_GLB_CTRL to mux sys-led peripheral |
-| GPIO1 |  | 1 | N/A | No known alternative functions |
+| RTL8231 MIIM bus |  | 1 | MDC  |  |
-| RTL8231 MIIM bus |  | 2 | MDC  |  |
+| :::              |  | 2 | MDIO | ::: |
-| :::              |  | 3 | MDIO | ::: |
+| JTAG |  | 3 | TMS   | Set JTAG_SEL to 0 (default) for JTAG, 2 for GPIO |
-| UART1 |  | 6 | RX | Set JTAG_SEL to 1 for UART1, 2 for GPIO |
-| :::   |  | 7 | TX | ::: |
-| JTAG |  |  | TMS   | Set JTAG_SEL to 0 (default) for JTAG, 2 for GPIO |
 | :::  |  | 4 | TCK   | ::: |
-| :::  |  |  | /TRST | ::: |
+| :::  |  | 5 | /TRST | ::: |
-| :::  |  | 7 | TDO   | ::: |
 | :::  |  | 6 | TDI   | ::: |
+| :::  |  | 7 | TDO   | ::: |
+| UART1 |  | 3 | /RTS | Set JTAG_SEL to 1 for UART1, 2 for GPIO |
+| :::   |  | 4 | /CTS | ::: |
+| :::   |  | 6 | RXD   | ::: |
+| :::   |  | 7 | TXD   | ::: |
+| SPI CS |  | 8 | /CS2 | Set SPI_CS_IF_SEL to 1 for extra chip selects, 0 for GPIO |
+| :::    |  | 9 | /CS3 | ::: |
+| IEEE 1588 |  | 12 |  | OUTPUT_1588_SEL |
 ===== External GPIO =====
 The SoCs have been designed with the [[RTL8231]] GPIO expanders in mind as a first-class citizen.
-A hardware peripheral is present that can keep track of the state of one (or two on RTL9310) RTL8231 chip(s).
+A hardware peripheral is present that can keep track of the state of one (or two on RTL93xx) RTL8231 chip(s).
+The SoC's have dedicated pins and controllers for this task. For rtl930x B6 `EXT_GPIO_MDIO` and A5 `EXT_GPIO_MDC` For rtl931x, AM25: `GPIO_MDC` and AL25: `GPIO_MDIO`. This does require the RTL8231 connected to only function as GPIO expander. This should not be confused with the dedicated `LED_MDxx` pins!
 To allow direct access to the devices, a raw command can be sent. For RTL8380 and RTL8390, there is no indication of request failure. RTL9300 and RTL9310 do have a flag to indicate failed read commands.
@@ Line 77: / Line 89: @@
 | 0x1188 | ISR_LOW    | Interrupt status register |
 | 0x118C | ISR_HIGH   | Interrupt status register |
+==== RTL930x muxing ====
+The RTL930x doesn't have a dedicated muxing section in the address space. Instead, the GPIO pin muxing is all over the SoC's addressing space, so this will be a challange. A dedicated page exists to inventory the [[rtl93xx:gpio_space|GPIO mux registers]].