SMP support

The switch SoCs use two MIPS architectures to provide symmetric multiprocessing (SMP):

• Dual VPE on RTL839x and RTL930x
• Dual CPU cores on RTL931x

RTL838x and older systems do not support SMP, as they only have one CPU core with a single VPE.

These CPUs use the MIPS CPU interrupt controller, combined with the Realtek interrupt controller, to manage interrupts from CPU peripherals and switch fabric. Each CPU has it's own MIPS interrupt controller and an instance of the Realtek interrupt controller.

Linux support for the interrupt controller will correctly manage the primary CPU interrupt controller, dynamically unmasking IRQ lines as they are requested by peripheral drivers. Any secondary VPE's interrupt controller however, will only start with IRQ 7 unmasked, i.e. the timer interrupt line. Since other interrupts were already enabled by the time the second VPE is brought online, this causes IRQs (coming through the SoC's interrupt controller) to not be handled by any secondary VPE. This is an issue especially when one wants to use the a Realtek timer for system interrupts instead of the R4K timer.

TODO provide some references.

Using the MIPS InterAptiv architecture with a GIC, these setups should be fully supported by upstream Linux MIPS support.