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rtl83xx [2020/09/18 22:49] – biot | rtl83xx [2022/12/30 15:47] (current) – svanheule | ||
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- | === Realtek RTL83xx series=== | ||
- | ^ Chip ^ Codename | + | ====== RTL83xx |
- | | [[rtl8370 | 8370]] | | 8051 | 8 GE, embedded phy | The 8051 core can be disabled for running unmanaged | | + | |
- | | [[rtl8370 | 8376]] | + | |
- | | [[8332M]] | + | |
- | | [[RTL838x | 8380M]] | + | |
- | | [[RTL838x | 8382M]] | + | |
- | | [[RTL838x | 8382L]] | + | |
- | | [[8351M]] | + | |
- | | [[8352M]] | + | |
- | | [[8353M]] | + | |
- | | [[8390M]] | + | |
- | | [[8391M]] | + | |
- | | [[8392M]] | + | |
- | | [[8393M]] | + | |
- | === Links === | + | ===== RTL837x series ===== |
+ | Lightweight managed, or unmanaged switch chips. | ||
+ | |||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[rtl8370 | 8370]] | ||
+ | | [[rtl8370 | 8376]] | ||
+ | |||
+ | ===== Realtek ESW/SSW ===== | ||
+ | Older SoCs, predating Maple and Cypress. Not supported. | ||
+ | |||
+ | ==== RTL8328/ | ||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[8328M]] | ||
+ | | [[8328S]] | ||
+ | | [[8328L]] | ||
+ | | [[8329M]] | ||
+ | | [[8377M]] | ||
+ | | [[8389L]] | ||
+ | | [[8389M]] | ||
+ | |||
+ | |||
+ | ===== Realtek Maple ===== | ||
+ | Single core MIPS 4KEc CPU, up to 28 ports. | ||
+ | |||
+ | ==== RTL833x series ==== | ||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[8330M]] | ||
+ | | [[8332M]] | ||
+ | |||
+ | ==== RTL838x series ==== | ||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[RTL838x | 8380M]] | Maple | RTL8380 | MIPS 4KEc @ 500MHz | 8 GE, 2 SFP | 8 internal PHYs (8218b), 2 Serdes | [[https:// | ||
+ | | [[RTL8381M]] | ||
+ | | [[RTL838x | 8382M]] | Maple | RTL8380 | MIPS 4KEc @ 500MHz | Up to 28 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https:// | ||
+ | | [[RTL838x | 8382L]] | Maple | RTL8380 | MIPS 4KEc @ 500MHz | Unmanaged | ||
+ | |||
+ | ==== Pin assignment ==== | ||
+ | The following pinout is the RTL8380, but it's expected considering the identical chip dimensions that the pinout is identical for all 833x/ | ||
+ | |||
+ | ^ Pin ^ Mux 0 ^ Mux 1 ^ Mux 2 ^ | ||
+ | |28|JTAG_TCK||GPIO13| | ||
+ | |29|JTAG_TMS||GPIO12| | ||
+ | |30|JTAG_TDO||GPIO10| | ||
+ | |31|JTAG_TDI||GPIO11| | ||
+ | |32|JTAG_TRST# | ||
+ | |110|GPIO03||| | ||
+ | |111|GPIO02||| | ||
+ | |112|GPIO01||| | ||
+ | |113|GPIO00|SYS_LED|| | ||
+ | |114|RESET# | ||
+ | |116|SSPI_CS# | ||
+ | |117|SSPI_SO|UART1_TX|| | ||
+ | |118|SSPI_SI|I2C_DAT|| | ||
+ | |119|SSPI_CLK|I2C_CLK|| | ||
+ | |120|MDIO_MDC||| | ||
+ | |121|MDIO_MDIO||| | ||
+ | |122|LED_CLK||| | ||
+ | |123|LED_DAT||| | ||
+ | |124|UART0_TX||| | ||
+ | |125|UART0_RX||| | ||
+ | |127|SPI_CS# | ||
+ | |128|SPI_SI/ | ||
+ | |129|SPI_SO/ | ||
+ | |130|SPI_CLK||| | ||
+ | |||
+ | ====== RTL8380M Serdes ====== | ||
+ | We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed. | ||
+ | ^ SerDes ^ Switch Ports ^ MII name ^ Notes ^ | ||
+ | | - | 0-7 | internal | | | ||
+ | | 0 | 8-11 | QSGMII | ||
+ | | 1 | 12-15 | QSGMII | ||
+ | | 2 | 16 | RSGMII | ||
+ | | 3 | 17 | SGMII | | | ||
+ | | - | 18 | internal | CPU NIC | | ||
+ | |||
+ | ====== RTL8381M Serdes ====== | ||
+ | We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed. | ||
+ | ^ SerDes ^ Switch Ports ^ MII name ^ Notes ^ | ||
+ | | - | 0-7 | internal | | | ||
+ | | 0 | 8 | SGMII | | | ||
+ | | 1 | 9 | SGMII | | | ||
+ | | 2 | 10-13 | QSGMII | ||
+ | |||
+ | ====== RTL8382M Serdes ====== | ||
+ | We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed. | ||
+ | ^ SerDes ^ Switch Ports ^ MII name ^ Notes ^ | ||
+ | | 0 | 0-3 | QSGMII | ||
+ | | 1 | 3-7 | QSGMII | ||
+ | | - | 8-15 | Internal | | ||
+ | | 2 | 16-19 | QSGMII | ||
+ | | 3 | 20-23 | QSGMII | ||
+ | | 4 | 24-25 | QSGMII | ||
+ | | 5 | 26-27 | RSGMII | ||
+ | |||
+ | ===== Realtek Cypress ===== | ||
+ | Dual threaded (VPE) MIPS34Kc CPU, supporting up to 52 ports. | ||
+ | |||
+ | ==== RTL835x series ==== | ||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[8351M]] | ||
+ | | [[8352M]] | ||
+ | | [[8353M]] | ||
+ | |||
+ | |||
+ | ==== RTL839x series ==== | ||
+ | ^ Chip ^ Codename ^ Series | ||
+ | | [[8391M]] | ||
+ | | [[8392M]] | ||
+ | | [[8393M]] | ||
+ | | [[8396M]] | ||
+ | |||
+ | |||
+ | ===== Links ===== | ||
* [[https:// | * [[https:// | ||
* A series of leaked documents is available in '' | * A series of leaked documents is available in '' | ||