| [[RTL8381M]] | | RTL8380 | MIPS 4KEc @ 500MHz | Up to 14 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8381m-vb-cg|Product page]] |
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| [[RTL838x | 8382M]] | Maple | RTL8380 | MIPS 4KEc @ 500MHz | Up to 28 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8381m-vb-cg-2|Product page]] |
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| [[RTL838x | 8382L]] | Maple | RTL8380 | MIPS 4KEc @ 500MHz | Unmanaged | 8 internal GE PHYs, no SDRAM interface | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8382l-vb-cg-2|Product page ]] |
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==== Pin assignment ====
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The following pinout is the RTL8380, but it's expected considering the identical chip dimensions that the pinout is identical for all 833x/838x.
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^ Pin ^ Mux 0 ^ Mux 1 ^ Mux 2 ^
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|28|JTAG_TCK||GPIO13|
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|29|JTAG_TMS||GPIO12|
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|30|JTAG_TDO||GPIO10|
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|31|JTAG_TDI||GPIO11|
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|32|JTAG_TRST#||GPIO14|
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|110|GPIO03|||
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|111|GPIO02|||
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|112|GPIO01|||
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|113|GPIO00|SYS_LED||
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|114|RESET#|||
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|116|SSPI_CS#|UART1_RX||
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|117|SSPI_SO|UART1_TX||
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|118|SSPI_SI|I2C_DAT||
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|119|SSPI_CLK|I2C_CLK||
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|120|MDIO_MDC|||
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|121|MDIO_MDIO|||
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|122|LED_CLK|||
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|123|LED_DAT|||
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|124|UART0_TX|||
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|125|UART0_RX|||
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|127|SPI_CS#0|||
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|128|SPI_SI/SIO0|||
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|129|SPI_SO/SIO1|||
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|130|SPI_CLK|||
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====== RTL8380M Serdes ======
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We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
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^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
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| - | 0-7 | internal | |
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| 0 | 8-11 | QSGMII | |
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| 1 | 12-15 | QSGMII | |
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| 2 | 16 | RSGMII | |
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| 3 | 17 | SGMII | |
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| - | 18 | internal | CPU NIC |
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====== RTL8381M Serdes ======
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We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
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^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
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| - | 0-7 | internal | |
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| 0 | 8 | SGMII | |
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| 1 | 9 | SGMII | |
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| 2 | 10-13 | QSGMII | |
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====== RTL8382M Serdes ======
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We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
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^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
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| 0 | 0-3 | QSGMII | |
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| 1 | 3-7 | QSGMII | |
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| - | 8-15 | Internal |
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| 2 | 16-19 | QSGMII | |
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| 3 | 20-23 | QSGMII | |
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| 4 | 24-25 | QSGMII | Can be combined with serdes 5 |
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| 5 | 26-27 | RSGMII | Can be combined with serdes 4|
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===== Realtek Cypress =====
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Dual threaded (VPE) MIPS34Kc CPU, supporting up to 52 ports.