Differences

This shows you the differences between two versions of the page.

--- rtl83xx [2022/01/16 19:10] – More product page links raylynnknight
+++ rtl83xx [2022/12/30 15:47] (current) – svanheule
@@ Line 1: / Line 1: @@
-=== Realtek RTL83xx series===
-^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
+====== RTL83xx series ======
+===== RTL837x series =====
+Lightweight managed, or unmanaged switch chips.
+^ Chip                ^ Codename ^ Series  ^ CPU core            ^ Ports             ^ Comment ^ References ^
 | [[rtl8370 | 8370]]  |          |         | 8051               | 8 GE, embedded phy | |
 | [[rtl8370 | 8376]]  |          |         | 8051               | Up to 16 GE, 8 embedded PHY | |
-| **832x** | | | | | | |
+===== Realtek ESW/SSW =====
+Older SoCs, predating Maple and Cypress. Not supported.
+==== RTL8328/8389 series ====
+^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
 | [[8328M]]           | ESW      | RTL8328 |                    | FE  |  |
 | [[8328S]]           | ESW      | RTL8328 |                    | FE  |  |
 | [[8328L]]           | ESW      | RTL8328 |                    | FE? |  |
 | [[8329M]]           | SSW      | RTL8389 |                    | FE? |  |
-| **833x** | | | | | | |
+| [[8377M]]           | SSW      | RTL8389 |                    | FE  |  |
+| [[8389L]]           | SSW      | RTL8389 |                    | FE ? |  |
+| [[8389M]]           | SSW      | RTL8389 |                    | FE ? |  |
+===== Realtek Maple =====
+Single core MIPS 4KEc CPU, up to 28 ports.
+==== RTL833x series ====
+^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
 | [[8330M]]           | Maple    | RTL8380 | MIPS 4KEc @ 500MHz | Up to 8 FE, 2GE  | 8 internal PHYs, 2 Serdes | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8330m-vb-cg|Product page]] |
 | [[8332M]]           | Maple    | RTL8380 | MIPS 4KEc @ 500MHz | Up to 24 FE, 4GE  | 8 internal PHYs, 4 Serdes | [[https://rtitwww.realtek.com/en/products/communications-network-ics/item/rtl8332m-vb-cg|Product page]] |
-| **837x** | | | | | | |
-| [[8377M]]           | SSW      | RTL8389 |                    | FE  |  |
+==== RTL838x series ====
-| **838x** | | | | | | |
+^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
 | [[RTL838x | 8380M]] | Maple    | RTL8380 | MIPS 4KEc @ 500MHz | 8 GE, 2 SFP | 8 internal PHYs (8218b), 2 Serdes | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8380m-vb-cg|Product page ]]|
-| [[8381M]]           |          | RTL8380 | MIPS 4KEc @ 500MHz | Up to 14 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8381m-vb-cg|Product page]] |
+| [[RTL8381M]]        |          | RTL8380 | MIPS 4KEc @ 500MHz | Up to 14 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8381m-vb-cg|Product page]] |
 | [[RTL838x | 8382M]] | Maple    | RTL8380 | MIPS 4KEc @ 500MHz | Up to 28 GE | 8 internal, 2 SGMII, 1 QSGMII | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8381m-vb-cg-2|Product page]] |
 | [[RTL838x | 8382L]] | Maple    | RTL8380 | MIPS 4KEc @ 500MHz | Unmanaged   | 8 internal GE PHYs, no SDRAM interface | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8382l-vb-cg-2|Product page ]] |
-| [[8389L]]           | SSW      | RTL8389 |                    | FE ? |  |
-| [[8389M]]           | SSW      | RTL8389 |                    | FE ? |  |
+==== Pin assignment ====
-| **835x** | | | | | | |
+The following pinout is the RTL8380, but it's expected considering the identical chip dimensions that the pinout is identical for all 833x/838x.
+^ Pin ^ Mux 0 ^ Mux 1 ^ Mux 2 ^
+|28|JTAG_TCK||GPIO13|
+|29|JTAG_TMS||GPIO12|
+|30|JTAG_TDO||GPIO10|
+|31|JTAG_TDI||GPIO11|
+|32|JTAG_TRST#||GPIO14|
+|110|GPIO03|||
+|111|GPIO02|||
+|112|GPIO01|||
+|113|GPIO00|SYS_LED||
+|114|RESET#|||
+|116|SSPI_CS#|UART1_RX||
+|117|SSPI_SO|UART1_TX||
+|118|SSPI_SI|I2C_DAT||
+|119|SSPI_CLK|I2C_CLK||
+|120|MDIO_MDC|||
+|121|MDIO_MDIO|||
+|122|LED_CLK|||
+|123|LED_DAT|||
+|124|UART0_TX|||
+|125|UART0_RX|||
+|127|SPI_CS#0|||
+|128|SPI_SI/SIO0|||
+|129|SPI_SO/SIO1|||
+|130|SPI_CLK|||
+====== RTL8380M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| - | 0-7   | internal | |
+| 0 | 8-11  | QSGMII   | |
+| 1 | 12-15 | QSGMII   | |
+| 2 | 16    | RSGMII   | |
+| 3 | 17    | SGMII    | |
+| - | 18    | internal | CPU NIC |
+====== RTL8381M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| - | 0-7   | internal | |
+| 0 | 8     | SGMII    | |
+| 1 | 9     | SGMII    | |
+| 2 | 10-13 | QSGMII   | |
+====== RTL8382M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| 0 | 0-3   | QSGMII   |  |
+| 1 | 3-7   | QSGMII   |  |
+| - | 8-15  | Internal |
+| 2 | 16-19 | QSGMII   | |
+| 3 | 20-23 | QSGMII   | |
+| 4 | 24-25 | QSGMII   | Can be combined with serdes 5 |
+| 5 | 26-27 | RSGMII   | Can be combined with serdes 4|
+===== Realtek Cypress =====
+Dual threaded (VPE) MIPS34Kc CPU, supporting up to 52 ports.
+==== RTL835x series ====
+^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
 | [[8351M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | Up to 24FE, 4GE | No embedded PHY, 17.6 GBit switch cap | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8351m-vc-cg|Product page]] |
 | [[8352M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | Up to 56 FE     | |
 | [[8353M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | 48FE, 4 GE      | No embedded PHY, 17.6 GBit switch cap | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8353m-vc-cg|Product page]] |
-| **839x** | | | | | | |
-| [[8390M]]           | Cypress  | RTL8390 |                    | | |
+==== RTL839x series ====
+^ Chip                ^ Codename ^ Series  ^CPU core            ^ Ports             ^ Comment ^ References ^
 | [[8391M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | 24x GE, 4x Combo GE/SFP | No emb PHY 56GBit switch cap |[[https://www.realtek.com/en/products/communications-network-ics/item/rtl8391m-cg|Product page]] |
 | [[8392M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | 24x GE, (4x Combo GE/SFP or 2x SGMII/100Base-FX/1000Base-X) | No emb PHY 56GBit switch cap |[[https://www.realtek.com/en/products/communications-network-ics/item/rtl8392m-vc-cg|Product page]] |
@@ Line 32: / Line 113: @@
 | [[8396M]]           | Cypress  | RTL8390 | MIPS 34Kc @ 700MHz | 24x GE, 2x SFP+        | No emb PHY 88GBit switch cap | [[https://www.realtek.com/en/products/communications-network-ics/item/rtl8396m-vc-cg|Product page]] |
-=== Links ===
+===== Links =====
   * [[https://manualzz.com/doc/31627850/draft-datasheet | Draft datasheet]] for the [[rtl83xx | RTL8380M/RTL8382M/RTL8382L]].
   * A series of leaked documents is available in ''libc0607'''s git repo [[https://github.com/libc0607/Realtek_switch_hacking | here]].