Differences

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--- rtl83xx [2022/08/07 10:58] – Regroup page contents on SoC generation svanheule
+++ rtl83xx [2022/12/30 15:47] (current) – svanheule
@@ Line 3: / Line 3: @@
 ===== RTL837x series =====
-Unmanaged switch chips.
+Lightweight managed, or unmanaged switch chips.
 ^ Chip                ^ Codename ^ Series  ^ CPU core            ^ Ports             ^ Comment ^ References ^
@@ Line 67: / Line 67: @@
 |130|SPI_CLK|||
+====== RTL8380M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| - | 0-7   | internal | |
+| 0 | 8-11  | QSGMII   | |
+| 1 | 12-15 | QSGMII   | |
+| 2 | 16    | RSGMII   | |
+| 3 | 17    | SGMII    | |
+| - | 18    | internal | CPU NIC |
-===== Reatek Cypress =====
+====== RTL8381M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| - | 0-7   | internal | |
+| 0 | 8     | SGMII    | |
+| 1 | 9     | SGMII    | |
+| 2 | 10-13 | QSGMII   | |
+====== RTL8382M Serdes ======
+We have very limited information on these SerDes other then 'what is in the code' and what is in the block diagrams of the datasheets. Some salty grains are needed.
+^ SerDes ^ Switch Ports ^ MII name ^ Notes ^
+| 0 | 0-3   | QSGMII   |  |
+| 1 | 3-7   | QSGMII   |  |
+| - | 8-15  | Internal |
+| 2 | 16-19 | QSGMII   | |
+| 3 | 20-23 | QSGMII   | |
+| 4 | 24-25 | QSGMII   | Can be combined with serdes 5 |
+| 5 | 26-27 | RSGMII   | Can be combined with serdes 4|
+===== Realtek Cypress =====
 Dual threaded (VPE) MIPS34Kc CPU, supporting up to 52 ports.