A Serializer/DeSerializer (serdes) is a component that allows one to take multiple parallel inputs (wires, MII lines) and turn them into a serial output, of 2 wires (or 4 if using differential pairs). The upside of this approach is using less wires and less synchronization issues between wires. The downside is that these signals are much more sensitive as they need to push data much faster. As such, the SerDes on our realtek platforms for the 10GBit PHY/SFP+ runs at 10.3GHz! Compared to 2.5MHz on a 10Mbit link for example.

The realtek chips have a various number of SerDes controllers, one per 'connection'. An SFP page typically uses a SerDes, but an Octal PHY, such as the RTL8218D also can use just one or two SerDes links. This means one can connect 8 gigabit PHY's to a single 10Gbit SerDes for example, saving significantly in PCB traces and thus complexity.

The realtek serdes controllers are quite flexible, which can be understandable, each PCB is designed differently and different parameters are needed to ensure clean signals between the chips. This is even more so important on Direct Attached Copper (DAC) SFP modules, which basically extend the SerDes signals over Copper wires. As such, the serdes needs to be calibrated/tuned to match its use.

SerDes configuration seems to be 'somewhat' documented in the SDK hardware profiles.

The [[https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/openwrt-dev/loader/u-boot-2011.12/board/Realtek/switch/sdk/src/dal/longan/dal_longan_sds.c#L4142|SDK] has RX and TX calibration routines. While we seem to use some of them in our code right now, we only use them for very high-speed links (SFP modules only?). We also use fixed tables that we use to patch the serdes with. Could it be that these tables are generated from these calibration results, which are much faster (and constant anyway)?