Differences

This shows you the differences between two versions of the page.

--- zyxel_xgs1250-12 [2021/10/30 13:39] – Create page svanheule
+++ zyxel_xgs1250-12 [2022/04/30 19:07] – Add switch port mappings and initial port LED table svanheule
@@ Line 4: / Line 4: @@
 ===== Hardware =====
-  * [[rtl930x|RTL9302B]] SoC
+  * [[rtl93xx|RTL9302B]] SoC
   * Macronix MX25L12833F (16MB flash)
   * Winbond W613GU6MB-12 (128MB DDR3 SDRAM)
@@ Line 15: / Line 15: @@
 A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
+{{wiki:zyxel:xgs1250-12-top.jpg?200}}
+{{wiki:zyxel:xgs1250-12-bottom.jpg?200}}
+{{wiki:zyxel:xgs1250-12-rtl8231.jpg?200}}
+==== JTAG ====
+The board has an unpopulated eJTAG header J2. Similar to the [[GS1900-48]], nSRST and nTRST are configured such that the port is disabled. The following modifications make use of the eJTAG port possible:
+  * Add jumper across R155 to connect the nSRST pin.
+  * Move R156 to R151 to change the permanent pull-down into a pull-up.
+  * (optional) Modify the heatsink and add a 2×7 pin header (see picture)
+The header's VIO pin is a voltage reference, tied to VCC via a 1k resistor (R153). This pin cannot be used to source current and is only provided as voltage reference.
+{{wiki:zyxel:xgs1250-12-jtag-heatsink.jpg?400}}
+==== Port numbers ====
+The RTL9302 SoC supports 24 GbE ports, and four 10G ports.
+Device ports 1-8 are switch ports 0-7.
+Device ports 9-12 are switch port 24-27.
+^ Ports ^ LED index ^ LED comment ^
+| 1-8   | 0 | Amber component of anti-parallel amber/green LED |
+| 1-8   | 1 | Green component of anti-parallel amber/green LED |
 ==== Board details ====
 <file>
+------------------ Board Configuration ------------------
+****************************
+ ZYXEL XGS1250-12
+****************************
+============================
+ Board GPIO
+============================
+Device  Pin  Direction  Default  Current  Purpose
+------- ---- ---------- -------- -------- --------
+INT     0    OUT        0        0
+INT     1    IN         1        1        FAN_CONTROL
+INT     6    IN         1        0        HW_VER_BIT1
+INT     7    IN         1        1        HW_VER_BIT0
+INT     11   OUT        0        0        FAN_EN
+INT     15   OUT        0        0        TX_DIS_P11
+INT     16   IN         0        1        SFP_Present_P11
+INT     17   IN         0        1        SFP_LOS_P11
+INT     20   IN         0        0        TX_FAULT_P11
+INT     21   OUT        1        1        RESET_PHY
+INT     22   IN         1        1        RST_BTN_OUT
 ============================
  Board Configuration
@@ Line 90: / Line 137: @@
   * [[https://download.zyxel.com/XGS1250-12/datasheet/XGS1250-12_2.pdf | Product datasheet]]
-{{tag>zyxel}} {{tag>sfp_10g}} {{tag>nbase-t}}
+{{tag>zyxel}} {{tag>sfp_10g}} {{tag>nbase-t}} {{tag>jtag}}