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zyxel_xgs1250-12 [2022/04/18 15:30] – Add JTAG VIO description, header part number svanheulezyxel_xgs1250-12 [2023/01/24 08:09] (current) oliver
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 The XGS1250-12 is a 11 + 1-port Multi-Gigabit L3 switch. It has 8 Gigabit ports, three 2.5/5/10GBit Ethernet ports and one SFP+ 10GBit uplink cages. The XGS1250-12 is a 11 + 1-port Multi-Gigabit L3 switch. It has 8 Gigabit ports, three 2.5/5/10GBit Ethernet ports and one SFP+ 10GBit uplink cages.
 +
 +{{ ::xgs1250.jpg?direct&600 |}}
  
 ===== Hardware ===== ===== Hardware =====
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 Power is supplied via a 12V 2A standard barrel connector. At the right side behind the grid is UART serial connector. Power is supplied via a 12V 2A standard barrel connector. At the right side behind the grid is UART serial connector.
 A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1. A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
 +
 +{{wiki:zyxel:xgs1250-12-top.jpg?200}}
 +{{wiki:zyxel:xgs1250-12-bottom.jpg?200}}
 +{{wiki:zyxel:xgs1250-12-rtl8231.jpg?200}}
  
 ==== JTAG ==== ==== JTAG ====
  
-The board has an unpopulated eJTAG header J2. Similar to the [[GS1900-48]], nSRST and nTRST are configured such that the port is disabled. The following modifications should make use of the eJTAG port possible (untested):+The board has an unpopulated eJTAG header J2. Similar to the [[GS1900-48]], nSRST and nTRST are configured such that the port is disabled. The following modifications make use of the eJTAG port possible:
   * Add jumper across R155 to connect the nSRST pin.   * Add jumper across R155 to connect the nSRST pin.
   * Move R156 to R151 to change the permanent pull-down into a pull-up.   * Move R156 to R151 to change the permanent pull-down into a pull-up.
-  * Add 2×7 pin header.+  * (optional) Modify the heatsink and add a 2×7 pin header (see picture)
  
 The header's VIO pin is a voltage reference, tied to VCC via a 1k resistor (R153). This pin cannot be used to source current and is only provided as voltage reference. The header's VIO pin is a voltage reference, tied to VCC via a 1k resistor (R153). This pin cannot be used to source current and is only provided as voltage reference.
  
-==== Board details ====+{{wiki:zyxel:xgs1250-12-jtag-heatsink.jpg?400}}
  
-{{wiki:zyxel:xgs1250-12-top.jpg?200}} +==== Port numbers ==== 
-{{wiki:zyxel:xgs1250-12-bottom.jpg?200}} + 
-{{wiki:zyxel:xgs1250-12-rtl8231.jpg?200}}+The RTL9302 SoC supports 24 GbE ports, and four 10G ports. 
 + 
 +Device ports 1-8 are switch ports 0-7
 +Device ports 9-12 are switch port 24-27
 + 
 +^ Ports ^ LED index ^ LED comment ^ 
 +| 1-8   | 0 | Amber component of anti-parallel amber/lime LED. LED0 must be off. | 
 +| 1-8   | 1 | Green component of anti-parallel amber/lime LED. LED1 must be off. | 
 +^ Ports ^ LED index ^ LED comment ^ 
 +| 9-11  | 0 | Multi-LED selection. 0 chooses the lime/amber LEDs. 1 chooses the RGB LEDs. | 
 +| 9-11  | 1 | LED0 = 0amber, LED0 = 1red | 
 +| 9-11  | 2 | LED0 = 0: lime, LED0 = 1: green | 
 +| 9-11  | 3 | LED0 = 0: (none), LED0 = 1: blue | 
 +^ Ports ^ LED index ^ LED comment ^ 
 +| 12    | 0 | Blue | 
 +| 12    | 1 | Lime | 
 + 
 +==== Board details ====
  
 <file> <file>
  • zyxel_xgs1250-12.1650295833.txt.gz
  • Last modified: 2022/04/18 15:30
  • by svanheule