Hasivo S1100WP-8GT_SE

The S1100WP-8GT_SE is an 8-port Multi-Gigabit L3 switch. It has 8 2.5GbE ports, and supports 802.3af/at on all ports, alongside 802.3bt on Port 1 out of the box. PoE is provided by a pair of HS104PTI chips, which are capable of supporting 802.3bt (90W) on each port.. however hardware constraints including trace thickness would be a limit (hence why 802.3bt defaults to port 1, shortest trace length)

Power is supplied via a 52V barrel connector.

Out of the box configuration is:

  • IP: 192.168.0.1
  • Subnet: 255.255.255.0
  • TFTP server: 192.168.0.111

PoE config:

  • Port 1: 802.3bt
  • Port 2: 802.3at
  • Port 3: 802.3at
  • Port 4: 802.3at
  • Port 5: 802.3at
  • Port 6: 802.3at
  • Port 7: 802.3at
  • Port 8: 802.3at

ESC during Uboot to enter password prompt Password is 'Hs2021cfgmg'

SoC

Pin(s) GPIO Alt Func Description
B1/B2 n/a UART0_TXD/UART0_RXD UART0 Tx/Rx to RS232 transceiver for console port
B5 GPIO0 n/a SYS LED (Green)
A14 GPIO19 n/a LED HC595 RCLK Output
A16 GPIO23 n/a ???, has internal pulldown, but reads high when idle
AG23,AF23,AG25,AF25 n/a HSOP_S2,HSON_S2,HSIP_S2,HSIN_S2 SerDes 2 to RTL8221B Port 0 PHY
AD26,AD27,AB26,AB27 n/a HSOP_S3,HSON_S3,HSIP_S3,HSIN_S3 SerDes 3 to RTL8221B Port 8 PHY
V27,V26,T27,T26 n/a HSOP_S4,HSON_S4,HSIP_S4,HSIN_S4 SerDes 4 to RTL8221B Port 16 PHY
P26,P27,M26,M27 n/a HSOP_S5,HSON_S5,HSIP_S5,HSIN_S5 SerDes 5 to RTL8221B Port 20 PHY
K27,K26,H27,H26 n/a HSOP_S6,HSON_S6,HSIP_S6,HSIN_S6 SerDes 6 to RTL8221B Port 24 PHY
F26,F27,D26,D27 n/a HSOP_S7,HSON_S7,HSIP_S7,HSIN_S7 SerDes 7 to RTL8221B Port 25 PHY
A25,B25,A23,B23 n/a HSOP_S8,HSON_S8,HSIP_S8,HSIN_S8 SerDes 8 to RTL8221B Port 26 PHY
B21,A21,B19,A19 n/a HSOP_S9,HSON_S9,HSIP_S9,HSIN_S9 SerDes 9 to RTL8221B Port 27 PHY
E2,H1,H2,G2,G1,F2,F1 n/a SPI_MST_CS[0], SPI_MST_… SPI Master Interface to Flash Memory
AD23,AE24 n/a M0_MDC,M0_MDIO MDIO 0 Interface to [1]PHY0,[2]PHY8,[3]PHY16,[4]PHY20
AG27,AF27 n/a M1_MDC,M1_MDIO MDIO 1 Interface to [1]PHY24,[2]PHY25,[3]PHY26,[4]PHY27
N1,U2,M2,U1,M1,V1,N2,V2,AA1,K1,Y2,J2,Y1,K2,W2,L1 n/a MD[15:0] DDR3 SDRAM Data Input/Output
AE8,AE1,AF4,AF1,AD2,AB1,AG4,AD1,AG5,AC2,AF6,AC1,AG6,AG3,AE2,AF3 n/a MA[15:0] DDR3 SDRAM Address Outputs
AG2,AB2,AF7 n/a BA[2:0] DDR3 SDRAM Bank Address Outputs
n/a DDR3 other signals

HC595

Chip Pin Description
U22 Qa lan8 LED 0 (?)
U22 Qb lan8 LED 1 (?)
U22 Qc lan8 LED 2 (?)
U22 Qd lan7 LED 0 (?)
U22 Qe lan7 LED 1 (?)
U22 Qf lan7 LED 2 (?)
U22 Qg lan6 LED 0 (?)
U22 Qh lan6 LED 1 (?)
U21 Qa lan6 LED 2 (?)
U21 Qb lan5 LED 0 (?)
U21 Qc lan5 LED 1 (?)
U21 Qd lan5 LED 2 (?)
U21 Qe lan4 LED 0 (?)
U21 Qf lan4 LED 1 (?)
U21 Qg lan4 LED 2 (?)
U21 Qh lan3 LED 0 (?)
U20 Qa lan3 LED 1 (?)
U20 Qb lan3 LED 2 (?)
U20 Qc lan2 LED 0 (?)
U20 Qd lan2 LED 1 (?)
U20 Qe lan1 LED 2 (?)
U20 Qf lan1 LED 0 (?)
U20 Qg lan1 LED 1 (?)
U20 Qh lan1 LED 2 (?)

PoE 8051

Pin Description
P3.0 UART RxD
P3.1 UART TxD
P3.2 PoE SCK
P3.3 PoE SDA
P3.4 lan1 PoE LED (active low)
P3.5 lan2 PoE LED (active low)
P3.6 lan3 PoE LED (active low)
P3.7 lan4 PoE LED (active low)
P1.0 lan5 PoE LED (active low)
P1.1 lan6 PoE LED (active low)
P1.6 lan7 PoE LED (active low)
P1.7 lan8 PoE LED (active low)
P5.5 FAN PWM (FET not populated)

console boot

uboot version

uboot printenv

uboot flshow

uboot flshow

uboot show hw_profile_list

uboot show tech-support

  • s1100wp-8gt_se.txt
  • Last modified: 2023/03/26 05:51
  • by bevanweiss