All information in this page is curated from the SDK sources (which are known to contain errors) or trial and error. Do not assume anything on this page is perfectly correct!

All SoCs in this series have a 34Kc MIPS core.

The picture below draws the clock tree as per documentation. What is unclear and obviously missing, is the SRAM PLL, which we do find in the sdk.

While the documentation speaks of an optional 156.25 Mhz Clock, no pintout seems to match this.

The Flattened Clock generator (as the SDK calls it).

• PLL0 / OCP0 / CPU

The realtek memory map is like like spaghetti, where registers are all over the place. Some things are almost logical, but not when looking at Linux based frameworks. The following table gives an overview of where to expect certain register:bits for a specific peripheral.

Interrupts are a bit more complex with both an interrupt and a routing component. See SoC interrupt controller for details.

The memory map addresses are obtained from a combination of the devicetree and the memory_map header

OCP* Directly connected to the CPU address bus

The SoC Peripherial map and register map. To read from U-Boot an offset of `0xb8000000` where linux accesses the uncached `0x18000000` is required to address registers via kseg1.

Could be likely the strapping pins or configuration registers

Could be likely the strapping pins

SoC series with condename "Longan".

Common features:

• Single core MIPS 34Kc with dual threading @ 800MHz
• 1.5MB of packet buffer

As we only have the datasheet for the RTL9301, this is the only hard evidence for the device due to pinouts that we know. Also important to note, that Only SserDes 2, 4, 6 and 8 have differential clock-pairs. There's also 4 single pole clock outputs.

The 9301 can also be configured in cascading mode, where the master or slave, uses the following serdes layout

As we have no datasheet for the RTL9302, this is based from code and 'how it seems to work', so some salt grains are needed here. Some unknowns are, we have 152 Gbit, or 76 GBit FD, and know that at most, we have to do 16 * 1GE, 8 * 2.5GE and 4 * 10GE. We also know that XGS1210/1250 use the last 4 serdes for those non-GE ports, and sds2 for an octal PHY using port 0 - 7. We also know we can't change port and serdes numbers, they are matched. It thus seems likely, considering the 9301 and minimal changes, that sds0 and 1 have been 'repurposed' for quad 2.5G serdes (10G), as we need to put 8x2.5 somewhere, again, can't change port numbers. We also know, that sds6-9 are single port serdeses, so the following table seems possible.

As we have no datasheet for the RTL9303, this is based from code and 'how it seems to work', so some salt grains are needed here.

Serdes 4 and 5 only map 4 ports each, unless this is configurable, we'd have to assume the rtl9303 doesn't support octal PHY's on those serdeses.

The following pinout is the RTL9301, but it's expected considering the identical chip dimensions that the pinout is identical for all 930x.

The RTL93xx doesn't have a pin mux in a traditional sense. While previous generations seems to have had it, the rtl930x seems to remove the notion entirely. Instead, control blocks have a (usually) single bit, indicating if a certain pad is to be setup as GPIO in (usually `0b0`, the default) or whatever special function the pad is part of (usually `0b1` to enable the pad as special function).

The following section describes the Mango, or rtl931x series. A lot of the things are duplicated from the rtl930x however, and thus only differences are explicitly mentioned here. Note though that this all grows organically however.

SoC series with codename "Mango". All SoCs in this series have a 1004Kc MIPS core.

Common features:

• Dual core MIPS InterAptiv @ 1GHz
• 2MB of packet buffer

The following pinout is the RTL9311, but it's expected considering the identical chip dimensions that the pinout is identical for all 931x.

Dedicated pins to serdes, PCIe etc are left out for briefety

Interrupts are a bit more complex with both an interrupt and a routing component. See SoC interrupt controller for details.

Configuration tables for 0x13bc (2 different views)

Why are there ports missing?