SoC interrupt controller

On the RTL8380, RTL8390, and RTL9300 families, interrupts from SoC peripherals are handled by the SoC interrupt controller. This controller can connect interrupt outputs from up to 32 peripherals to the six MIPS CPU hardware interrupts. The way these interrupts are routed is runtime configurable, allowing for some flexibility between different SoC families and board designs.

The RTL9310 family of SoCs is based on MIPS InterAptiv, and uses a GIC to manage SoC interrupts.

Each interrupt controller block has 32 SoC interrupt input lines, and each of these inputs can be routed to one of the connected parent interrupts by configuring the routing registers. On all SoCs, these parent interrupts are the MIPS CPU hardware interrupts (IRQ2-IRQ7).

SoC IRQ  +------+  Parent IRQs
source   |     -|-----> CPU IRQ2
         |  /---|-----> CPU IRQ3
  >------|-/   -|-----> CPU IRQ4
         |     -|-----> CPU IRQ5
         |     -|-----> CPU IRQ6
         |     -|-----> CPU IRQ7 (timer)
         +------+

An independent interrupt controller block is present in the SoCs for each VPE (one on RTL8380, two on RTL8390 and RTL9300). In the diagram below, Peripheral A has two interrupt sources that are used to perform IRQ balancing between both VPEs. Peripheral B on the other hand, has only one interrupt output that is connected to both IRQ controllers, leaving CPU balancing to the interrupt controller. For consistency, a single peripheral is always connected to the same interrupt input on each interrupt controller.

SOC IRQ LINES                        MIPS
                       +-----------+ HW IRQ   +--------+
Peripheral A[CPU0]---->| SOC IRQ   | LINES    | IRQ    |
Peripheral B ------o-->| VPE0 CTRL |=========>| VPE0   |
        .          |   +-----------+          +--------+
        .          |
        .          |
                   |   +-----------+          +--------+
                   \-->| SOC IRQ   |          | IRQ    |  (Not available ont RTL8380)
Peripheral A[CPU1]---->| VPE1 CTRL |=========>| VPE1   |
                       +-----------+          +--------+

In theory, this architecture allows for peripheral interrupts to be routed to any one of that VPE's HW IRQs. For example, the GPIO interrupt line could be routed to IRQ4 on VPE0, and IRQ2 on VPE1. In order to perform sensible IRQ balancing, the same routing should be used in both IRQ controllers blocks.

While each MIPS processor has 5 interrupts internally, they should really be thought of as 'priority queues'. E.g. if UART0 is connected to VPE0 IRQ2, and UART1 is connected to VPE0 IRQ5, UART0 would have a higher priority due to it being routed to the higher priority IRQ on the VPE.

Each interrupt controller block has six registers, used to read interrupt status, and to route and enable interrupts.

Base addresses:

• RTL8380: 0x18003000
• RTL8390: 0x18003000 (VPE0), 0x18003018 (VPE1)
• RTL9300: 0x18003000 (VPE0), 0x18003018 (VPE1)