|
DEBUG_COUNTER
|
|---|
| b5b8 |
STAT_PRVTE_DROP_COUNTER0 |
|
| b5bc |
STAT_PRVTE_DROP_COUNTER1 |
|
| b5c0 |
STAT_PRVTE_DROP_COUNTER2 |
|
| b5c4 |
STAT_PRVTE_DROP_COUNTER3 |
|
| b5c8 |
STAT_PRVTE_DROP_COUNTER4 |
|
| b5cc |
STAT_PRVTE_DROP_COUNTER5 |
|
| b5d0 |
STAT_PRVTE_DROP_COUNTER6 |
|
| b5d4 |
STAT_PRVTE_DROP_COUNTER7 |
|
| b5d8 |
STAT_PRVTE_DROP_COUNTER8 |
|
| b5dc |
STAT_PRVTE_DROP_COUNTER9 |
|
| b5e0 |
STAT_PRVTE_DROP_COUNTER10 |
|
| b5e4 |
STAT_PRVTE_DROP_COUNTER11 |
|
| b5e8 |
STAT_PRVTE_DROP_COUNTER12 |
|
| b5ec |
STAT_PRVTE_DROP_COUNTER13 |
|
| b5f0 |
STAT_PRVTE_DROP_COUNTER14 |
|
| b5f4 |
STAT_PRVTE_DROP_COUNTER15 |
|
| b5f8 |
STAT_PRVTE_DROP_COUNTER16 |
|
| b5fc |
STAT_PRVTE_DROP_COUNTER17 |
L3_IPUC_NON_IP non-ip packets dropped that hit a router MAC. |
| b600 |
STAT_PRVTE_DROP_COUNTER18 |
|
| b604 |
STAT_PRVTE_DROP_COUNTER19 |
|
| b608 |
STAT_PRVTE_DROP_COUNTER20 |
|
| b60c |
STAT_PRVTE_DROP_COUNTER21 |
|
| b610 |
STAT_PRVTE_DROP_COUNTER22 |
|
| b614 |
STAT_PRVTE_DROP_COUNTER23 |
|
| b618 |
STAT_PRVTE_DROP_COUNTER24 |
|
| b61c |
STAT_PRVTE_DROP_COUNTER25 |
HOST_NULL_INTF, drops that are due to a DROP action in a Host Route … |
| b620 |
STAT_PRVTE_DROP_COUNTER26 |
|
| b624 |
STAT_PRVTE_DROP_COUNTER27 |
|
| b628 |
STAT_PRVTE_DROP_COUNTER28 |
|
| b62c |
STAT_PRVTE_DROP_COUNTER29 |
|
| b630 |
STAT_PRVTE_DROP_COUNTER30 |
|
| b634 |
STAT_PRVTE_DROP_COUNTER31 |
|
| b638 |
STAT_PRVTE_DROP_COUNTER32 |
|
| b63c |
STAT_PRVTE_DROP_COUNTER33 |
|
| b640 |
STAT_PRVTE_DROP_COUNTER34 |
|
| b644 |
STAT_PRVTE_DROP_COUNTER35 |
L3_UC_ICMP_REDIR, counts drops when the Egress interface … |
| b648 |
STAT_PRVTE_DROP_COUNTER36 |
|
| b64c |
STAT_PRVTE_DROP_COUNTER37 |
|
| b650 |
STAT_PRVTE_DROP_COUNTER38 |
|
| b654 |
STAT_PRVTE_DROP_COUNTER39 |
|
| b658 |
STAT_PRVTE_DROP_COUNTER40 |
|
| b65c |
STAT_PRVTE_DROP_COUNTER41 |
|
| b660 |
STAT_PRVTE_DROP_COUNTER42 |
|
| b664 |
STAT_PRVTE_DROP_COUNTER43 |
|
| b668 |
STAT_PRVTE_DROP_COUNTER44 |
|
| b66c |
STAT_PRVTE_DROP_COUNTER45 |
|
| b670 |
STAT_PRVTE_DROP_COUNTER46 |
|
| b674 |
STAT_PRVTE_DROP_COUNTER47 |
|
| b678 |
STAT_PRVTE_DROP_COUNTER48 |
|
| b67c |
STAT_PRVTE_DROP_COUNTER49 |
|
| b680 |
STAT_PRVTE_DROP_COUNTER50 |
|
| b684 |
STAT_PRVTE_DROP_COUNTER51 |
|
| b688 |
STAT_PRVTE_DROP_COUNTER52 |
TRUNK_FILTER packet is dropped because the L3 system tries to forward … |
| b68c |
STAT_PRVTE_DROP_COUNTER53 |
|
| b690 |
STAT_PRVTE_DROP_COUNTER54 |
|
| b694 |
STAT_PRVTE_DROP_COUNTER55 |
|
| b698 |
STAT_PRVTE_DROP_COUNTER56 |
|
| b69c |
STAT_PRVTE_DROP_COUNTER57 |
|
| b6a0 |
STAT_PRVTE_DROP_COUNTER58 |
|
| b6a4 |
STAT_PRVTE_DROP_COUNTER59 |
|
| b6a8 |
STAT_PRVTE_DROP_COUNTER60 |
|
| b6ac |
STAT_PRVTE_DROP_COUNTER61 |
|
| b6b0 |
STAT_PRVTE_DROP_COUNTER62 |
|
| b6b4 |
STAT_PRVTE_DROP_COUNTER63 |
|
| b6b8 |
STAT_PRVTE_DROP_COUNTER64 |
|
| b6bc |
STAT_PRVTE_DROP_COUNTER65 |
|
| b6c0 |
STAT_PRVTE_DROP_COUNTER66 |
|
| b6c4 |
STAT_PRVTE_DROP_COUNTER67 |
|
| b6c8 |
STAT_PRVTE_DROP_COUNTER68 |
|
| b6cc |
STAT_PRVTE_DROP_COUNTER69 |
|
| b6d0 |
STAT_PRVTE_DROP_COUNTER70 |
|
| b6d4 |
STAT_PRVTE_DROP_COUNTER71 |
|
| b6d8 |
STAT_PRVTE_DROP_COUNTER72 |
|
| b6dc |
STAT_PRVTE_DROP_COUNTER73 |
|
| b6e0 |
STAT_PRVTE_DROP_COUNTER74 |
|
| b6e4 |
STAT_PRVTE_DROP_COUNTER75 |
INVALID_L2_NEXTHOP_ENTRY An L3 nexthop entry points to an invalid L2 … |
| b6e8 |
STAT_PRVTE_DROP_COUNTER76 |
|
| b6ec |
STAT_PRVTE_DROP_COUNTER77 |
|
| b6f0 |
STAT_PRVTE_DROP_COUNTER78 |
|
| b6f4 |
STAT_PRVTE_DROP_COUNTER79 |
|
| b6f8 |
STAT_PRVTE_DROP_COUNTER80 |
|
| b6fc |
STAT_PRVTE_DROP_COUNTER81 |
|
| b700 |
STAT_PRVTE_DROP_COUNTER82 |
|
| b704 |
STAT_PRVTE_DROP_COUNTER83 |
|
| b708 |
STAT_PRVTE_DROP_COUNTER84 |
|
|
MAC_CONTROL
|
|---|
| ca00 |
SMI_GLB_CTRL |
Global control register of the SMI busses 0-3. |
| ca04 |
SMI_MAC_TYPE_CTRL |
|
| ca08 |
SMI_PORT0_15_POLLING_SEL |
SMI Port 0 - 15 polling selector |
| ca0c |
SMI_PORT16_27_POLLING_SEL |
SMI Port 16 - 27 polling selector |
| ca10 |
SMI_PRVTE_POLLING_CTRL |
SMI Private polling controller |
| ca14 |
MDIO_FREE_CNT_CTRL |
MDIO Free counter controller |
| ca18 |
SMI_10GPHY_POLLING_SEL_0 |
10G/2.5G GPHY internal resolution register |
| ca1c |
MAC_FORCE_MODE_CTRL |
Per port MAC force mode controller |
| ca90 |
SMI_POLL_CTRL |
|
| ca94 |
SMI_REG_CHK1_CTRL0 |
|
| ca98 |
SMI_REG_CHK1_CTRL1 |
|
| ca9c |
SMI_REG_CHK1_PMSK |
|
| caa0 |
SMI_REG_CHK1_DATA |
|
| caa4 |
SMI_REG_CHK1_DATA_10G |
|
| caa8 |
SMI_REG_CHK1_RESULT |
|
| caac |
SMI_REG_CHK2_CTRL0 |
|
| cab0 |
SMI_REG_CHK2_CTRL1 |
|
| cab4 |
SMI_REG_CHK2_PMSK |
|
| cab8 |
SMI_REG_CHK2_DATA |
|
| cabc |
SMI_REG_CHK2_DATA_10G |
|
| cac0 |
SMI_REG_CHK2_RESULT |
|
| cac4 |
SMI_REG_CHK3_CTRL0 |
|
| cac8 |
SMI_REG_CHK3_CTRL1 |
|
| cacc |
SMI_REG_CHK3_PMSK |
|
| cad0 |
SMI_REG_CHK3_DATA |
|
| cad4 |
SMI_REG_CHK3_DATA_10G |
|
| cad8 |
SMI_REG_CHK3_RESULT |
|
| cadc |
SMI_REG_CHK4_CTRL0 |
|
| cae0 |
SMI_REG_CHK4_CTRL1 |
|
| cae4 |
SMI_REG_CHK4_PMSK |
|
| cae8 |
SMI_REG_CHK4_DATA |
|
| caec |
SMI_REG_CHK4_DATA_10G |
|
| caf0 |
SMI_REG_CHK4_RESULT |
|
| caf4 |
SMI_REG_CHK5_CTRL0 |
|
| caf8 |
SMI_REG_CHK5_CTRL1 |
|
| cafc |
SMI_REG_CHK5_PMSK |
|
| cb00 |
SMI_REG_CHK5_DATA |
|
| cb04 |
SMI_REG_CHK5_DATA_10G |
|
| cb08 |
SMI_REG_CHK5_RESULT |
|
| cb0c |
LINK_DELAY_CTRL |
Link update delay controller |
| cb10 |
MAC_LINK_STS |
Link status as the MAC sees it. |
| cb14 |
MAC_LINK_MEDIA_STS |
|
| cb18 |
MAC_LINK_SPD_STS |
|
| cb28 |
MAC_LINK_DUP_STS |
|
| cb2c |
MAC_TX_PAUSE_STS |
|
| cb30 |
MAC_RX_PAUSE_STS |
|
| cb34 |
MAC_EEE_ABLTY |
|
| cb38 |
MAC_MSTR_SLV_STS |
|
| cb3c |
MAC_MSTR_SLV_FAULT_STS |
|
| cb40 |
PHY_LINK_STS |
|
| cb44 |
PHY_LINK_MEDIA_STS |
|
| cb48 |
PHY_LINK_SPD_STS |
|
| cb58 |
PHY_LINK_DUP_STS |
|
| cb5c |
PHY_TX_PAUSE_STS |
|
| cb60 |
PHY_RX_PAUSE_STS |
|
| cb64 |
PHY_EEE_ABLTY |
|
| cb68 |
PHY_MSTR_SLV_STS |
|
| cb6c |
PHY_MSTR_SLV_FAULT_STS |
|
| cb70 |
SMI_ACCESS_PHY_CTRL_0 |
PHY port select and PHY broadcast control register 0 |
| cb74 |
SMI_ACCESS_PHY_CTRL_1 |
|
| cb78 |
SMI_ACCESS_PHY_CTRL_2 |
|
| cb7c |
SMI_ACCESS_PHY_CTRL_3 |
|
| cb80 |
SMI_PORT0_5_ADDR_CTRL |
SMI port 0 - 5 address mapping controller |
| cb84 |
SMI_PORT6_11_ADDR_CTRL |
SMI port 6 - 11 address mapping controller |
| cb88 |
SMI_PORT12_17_ADDR_CTRL |
SMI port 12 - 17 address mapping controller |
| cb8c |
SMI_PORT18_23_ADDR_CTRL |
SMI port 18 - 23 address mapping controller |
| cb90 |
SMI_PORT24_27_ADDR_CTRL |
SMI port 24 - 27 address mapping controller |
| cb94 |
SDS_MODE_ADJ_CTRL |
|
| cb98 |
SMI_CTRL |
|
| cb9c |
EXT_SMI_ACCESS_CTRL |
|
| cba0 |
DMY_REG0_SMI_CTRL |
|
| cba4 |
RLFD_CTRL |
|
| cba8 |
RLFD_10G_ADDR |
|
| cbac |
UNI_DIR_CTRL |
|
| cbb0 |
SMI_10GPHY_POLLING_SEL_1 |
MDIO device and register address for polling the 10G/2G5 PHY internal … |
| cbb4 |
SMI_10GPHY_POLLING_REG0_CFG |
Reg 0 for polling 10G and 2G5 PHY |
| cbb8 |
SMI_10GPHY_POLLING_REG9_CFG |
Reg 9 for polling 10G and 2G5 PHY |
| cbbc |
SMI_10GPHY_POLLING_REG10_CFG |
Reg 10 for polling 10G and 2G5 PHY |
|
LED
|
|---|
| cc00 |
LED_GLB_CTRL |
External LED controller global register (of the RTL8231) |
| cc04 |
LED_PORT_NUM_CTRL |
Number of status LEDs per port |
| cc0c |
LED_SET3_1_CTRL |
LED set 3 control register (LED 2 and 3) |
| cc10 |
LED_SET3_0_CTRL |
LED set 3 control register (LED 0 and 1) |
| cc14 |
LED_SET2_1_CTRL |
LED set 2 control register (LED 2 and 3) |
| cc18 |
LED_SET2_0_CTRL |
LED set 2 control register (LED 0 and 1) |
| cc1c |
LED_SET1_1_CTRL |
LED set 1 control register (LED 2 and 3) |
| cc20 |
LED_SET1_0_CTRL |
LED set 1 control register (LED 0 and 1) |
| cc24 |
LED_SET0_1_CTRL |
LED set 0 control register (LED 2 and 3) |
| cc28 |
LED_SET0_0_CTRL |
LED set 0 control register (LED 0 and 1) |
| cc2c |
LED_PORT_COPR_SET_SEL_CTRL |
Copper port configuration set selection |
| cc34 |
LED_PORT_FIB_SET_SEL_CTRL |
Fiber port configuration set selection |
| cc3c |
LED_PORT_COPR_MASK_CTRL |
Port mask for copper-enabled ethernet ports |
| cc40 |
LED_PORT_FIB_MASK_CTRL |
Port mask for fiber-enabled ethernet ports |
| cc44 |
LED_PORT_COMBO_MASK_CTRL |
Port mask for combo ethernet ports |
| cc48 |
SW_LED_LOAD |
Commit software LED settings |
| cc4c |
LED_PORT_SW_EN_CTRL |
Bit mask indicating which LEDs are software controlled. |
| cc5c |
LED_PORT_SW_CTRL |
Configure a software controlled LED |
| cccc |
LED_INDRT_ACCESS_CTRL |
External LED indirect access controller (of the RTL8231) |
| ccd0 |
LED_LOAD_LV1_10G |
|
| ccd4 |
LED_LOAD_LV2_10G |
|
| ccd8 |
LED_LOAD_LV3_10G |
|
| ccdc |
LED_LOAD_LV1_5G |
|
| cce0 |
LED_LOAD_LV2_5G |
|
| cce4 |
LED_LOAD_LV3_5G |
|
| cce8 |
LED_LOAD_LV1_2P5G |
|
| ccec |
LED_LOAD_LV2_2P5G |
|
| ccf0 |
LED_LOAD_LV3_2P5G |
|
| ccf4 |
LED_LOAD_LV1_1G |
|
| ccf8 |
LED_LOAD_LV2_1G |
|
| ccfc |
LED_LOAD_LV3_1G |
|
| cd00 |
LED_LOAD_LV1_500M |
|
| cd04 |
LED_LOAD_LV2_500M |
|
| cd08 |
LED_LOAD_LV3_500M |
|
| cd0c |
LED_LOAD_LV1_100M |
|
| cd10 |
LED_LOAD_LV2_100M |
|
| cd14 |
LED_LOAD_LV3_100M |
|
| cd18 |
LED_LOAD_LV1_10M |
|
| cd1c |
LED_LOAD_LV2_10M |
|
| cd20 |
LED_LOAD_LV3_10M |
|
| cd24 |
LED_P_LOAD_CTRL |
|
| cd28 |
DMY_REG0_LED |
|