Realtek switch SoC docs

Control read/write protection of protected registers.

Main thermal meter control register.

Thermal measurement output register.

Chip revision number

SoC model identifier

CPU and SoC revision information

Extra GPIO MDIO bus control register.

Lexra clock control register.

Lexra clock control register.

Switch fabric clock control register.

Switch fabric clock control register.

Drive strength and slew rate control for I/O peripherals

ASIC configuration flags.

Per-Port Management Informaion Base counters, providing statistics …

Reset all MIB counters.

Resets the MIB statistics counters for a given port

Main L2 configuration register

Manage port flooding for broadcast and unknown unicast destinations.

Source address learning of L2 addresses

Per-port L2 (MAC) address learning.

Filter loopback packets where the ingress is equal to the egress port.

Defines on whether L2 lookup for forwarding is based on the inner or …

Defines an offset of the FID for all VLANs which do L2 lookup based on …

Per-port inner and outer PVID values

Port isolation control

Configuration for vlan-based port configuration

Configure which ports can exchange packets that have a specific VLAN …

Configure actions for Reserved Multicast Addresses

STP and VLAN bypass control for Reserved Multicast Addresses.

Control source MAC learning for RMA frames.

Low address bytes for arbitrary RMA rule

Custom control for arbitrary RMA

Low address bytes for arbitrary RMA rule

Custom control for arbitrary RMA

Custom 01-80-C2-00-00-xx RMA control

Custom 01-80-C2-00-00-xx RMA control

Custom 01-80-C2-00-00-xx RMA control

Custom 01-80-C2-00-00-xx RMA control

Per-port handling of BPDU frames

Per-port handling of PTP frames.

Per-port handling of LLDP frames

BPDU flooding port selection

Enable or disable power on a Packet Inspection Engine rule Block

Set the templates active in a given PIE block

Configuration of user-definable templates for the PIE

Used to clear a range of ACL rules

ALE_TX_GOOD_PKTS

MAC_RX_DROP

ACL_FWD_DROP

HW_ATTACK_PREVENTION_DROP

RMA_DROP

VLAN_IGR_FLTR_DROP

INNER_OUTER_CFI_EQUAL_1_DROP

PORT_MOVE_DROP

NEW_SA_DROP

MAC_LIMIT_SYS_DROP

MAC_LIMIT_VLAN_DROP

MAC_LIMIT_PORT_DROP

ACL_LKMISS_DROP

ACL_DROP

INBW_DROP

IGR_METER_DROP

ACCEPT_FRAME_TYPE_DROP

STP_IGR_DROP

INVALID_SA_DROP

SA_BLOCKING_DROP

Miscellaneous I/O control bits.

Set the LED behaviour for the low and high ports.

Control which ports have an associated (ASIC controlled) LED.

Control RTL8231 GPIO36 when using a scanning output mode

Bitmask indicating if LED0 is controlled by the user.

Bitmask indicating if LED1 is controlled by the user.

Bitmask indicating if LED2 is controlled by the user.

Set LED modes for a manually controlled switch port LED.

Auxiliary MDIO port access.

Auxiliary MDIO and extra GPIO device control register.

Direction shadow register for RTL8231 GPIOs 0-31

Direction shadow register for RTL8231 GPIOs 32-26

Data shadow register for RTL8231 GPIOs 0-31

Data shadow register for RTL8231 GPIOs 32-36

Link status as the MAC sees it.

MAC media connection type

MAC Link speed status

Size limits for packets being switched.

EEE TX timer control for 500M (‘Giga Lite’)